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1/3 preliminary data january 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. psd935g2 configurable memory system on a chip for 8-bit microcontrollers features summary 5 v10% single supply voltage: up to 4 mbit of primary flash memory (8 uniform sectors) 256kbit secondary flash memory (4 uniform sectors) up to 64 kbit sram over 3,000 gates of pld: dpld 52 reconfigurable i/o ports enhanced jtag serial port programmable power management high endurance: C 100,000 erase/write cycles of flash memory C 1,000 erase/write cycles of pld figure 1. packages tqfp80 (u)
1 1.0 introduction psd9xx family psd935g2 configurable memory system on a chip for 8-bit microcontrollers the psd9xx series of programmable microcontroller (mcu) peripherals brings in-system-programmability (isp) to flash memory and programmable logic. the result is a simple and flexible solution for embedded designs. psd9xx devices combine many of the peripheral functions found in mcu based applications: 4 mbit of flash memory a secondary flash memory for boot or data over 3,000 gates of flash programmable logic 64 kbit sram reconfigurable i/o ports programmable power management.
psd9xx family psd935g2 2 1.0 introduction (cont.) please refer to the revision block at the end of this document for updated information. the psd935g2 device offers two methods to program psd flash memory while the psd is soldered to a circuit board. in-system programming (isp) via jtag an ieee 1149.1 compliant jtag-isp interface is included on the psd enabling the entire device (both flash memories, the pld, and all configuration) to be rapidly programmed while soldered to the circuit board. this requires no mcu participation, which means the psd can be programmed anytime, even while completely blank. the innovative jtag interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: ? first time programming ? how do i get firmware into the flash the very first time? jtag is the answer, program the psd while blank with no mcu involvement. ? inventory build-up of pre-programmed devices ? how do i maintain an accurate count of pre-programmed flash memory and pld devices based on customer demand? how many and what version? jtag is the answer, build your hardware with blank psds soldered directly to the board and then custom program just before they are shipped to customer. no more labels on chips and no more wasted inventory. ? expensive sockets ? how do i eliminate the need for expensive and unreliable sockets? jtag is the answer. solder the psd directly to the circuit board. program first time and subsequent times with jtag. no need to handle devices and bend the fragile leads. in-application re-programming (iap) two independent flash memory arrays are included so the mcu can execute code from one memory while erasing and programming the other. robust product firmware updates in the field are possible over any communication channel (can, ethernet, uart, j1850, etc) using this unique architecture. designers are relieved of these problems: ? simultaneous read and write to flash memory ? how can the mcu program the same memory from which it is executing code? it cannot. the psd allows the mcu to operate the two flash memories concurrently, reading code from one while erasing and programming the other during iap. ? complex memory mapping ? how can i map these two memories efficiently? a programmable decode pld is embedded in the psd. the concurrent psd memories can be mapped anywhere in mcu address space, segment by segment with extremely high address resolution. as an option, the secondary flash memory can be swapped out of the system memory map when iap is complete. a built-in page register breaks the mcu address limit. ? separate program and data space ? how can i write to flash memory while it resides in ?rogram?space during field firmware updates, my 80c51 won? allow it the flash psd provides means to ?eclassify?flash memory as ?ata?space during iap, then back to ?rogram?space when complete. psdsoft ? st ? software development tool ?guides you through the design process step-by-step making it possible to complete an embedded mcu design capable of isp/iap in just hours. select your mcu and psdsoft will take you through the remainder of the design with point and click entry, covering...psd selection, pin definitions, programmable logic inputs and outputs, mcu memory map definition, ansi c code generation for your mcu, and merging your mcu firmware with the psd design. when complete, two different device programmers are supported directly from psdsoft flashlink (jtag) and psdpro. the psd935g2 is available in an 80-pin tqfp package.
psd935g2 psd9xx family a simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. the bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. a partial list of the mcu families supported include: intel 8031, 80196, 80188, 80c251 motorola 68hc11 and 68hc16 philips 8031 and 80c51xa zilog z80, z8 and z180 infineon c500 family 4 mbit flash memory. this is the main flash memory. it is divided into eight equal-sized blocks that can be accessed with user-specified addresses. internal secondary 256 kbit flash boot memory. it is divided into four equal-sized blocks that can be accessed with user-specified addresses. this secondary memory brings the ability to execute code and update the main flash concurrently. 64 kbit sram. the sram? contents can be protected from a power failure by connecting an external battery. general purpose pld (gpld) with 24 outputs. the gpld may be used to implement external chip selects or combinatorial logic function. decode pld (dpld) that decodes address for selection of internal memory blocks. 52 individually configurable i/o port pins that can be used for the following functions: mcu i/os pld i/os latched mcu address output special function i/os. i/o ports may be configured as open-drain outputs. standby current as low as 50 a for 5 v devices. built-in jtag compliant serial port allows full-chip in-system programmability (isp). with it, you can program a blank device or reprogram a device in the factory or the field. internal page register that can be used to expand the microcontroller address space by a factor of 256. internal programmable power management unit (pmu) that supports a low power mode called power down mode. the pmu can automatically detect a lack of microcontroller activity and put the psd9xx into power down mode. erase/write cycles: flash memory ?100,000 minimum pld ?1,000 minimum 2.0 key features 3 3.0 psd9xx series part # flash flash main boot serial isp memory memory psd9xx i/o pld input output pld jtag/isp kbit kbit sram supply series device pins inputs macrocells macrocells outputs port 8 sectors (4 sectors) kbit voltage psd935g2 52 66 24 yes 4096 256 64 5v psd9xx psd913g2 27 57 19 yes 1024 256 16 5v psd934f2 27 57 19 yes 2048 256 64 5v table 1. psd9xx product matrix
psd9xx family psd935g2 4 prog. mcu bus intrf. adio port cntl0, cntl1, cntl2 ad0 ad15 * pld input bus prog. port port a prog. port port b power mangmt unit 4 mbit main flash memory 8 sectors vstdby pa0 pa7 prog. port port f prog. port port g prog. port port e pb0 pb7 prog. port port c prog. port port d pf0 pf7 pg0 pg7 pe0 pe7 pc0 pc7 pd0 pd3 address/data/control bus 66 66 256 kbit secondary flash memory (boot or data) 4 sectors 64 kbit battery backup sram runtime control and i/o registers sram select gpld output gpld output gpld output i/o port pld input csiop flash isp pld (gpld) flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pe6 ) page register embedded algorithm sector selects sector selects global config. & security figure 1. psd935g2 block diagram * additional address lines can be brought into psd via port a, b, c, d, or f.
psd935g2 psd9xx family 5 psd9xx devices contain several major functional blocks. figure 1 on page 3 shows the architecture of the psd9xx device family. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions and are user configurable. 4.1 memory the psd935g2 contains the following memories: 4 mbit flash a secondary 256 kbit flash memory for boot or data 64 kbit sram. each of the memories is briefly discussed in the following paragraphs. a more detailed discussion can be found in section 9. the 4 mbit flash is the main memory of the psd935g2. it is divided into eight equally-sized sectors that are individually selectable. the 256 kbit secondary flash memory is divided into four equally-sized sectors. each sector is individually selectable. the 64 kbit sram is intended for use as a scratchpad memory or as an extension to the microcontroller sram. if an external battery is connected to the psd9xx? vstby pin, data will be retained in the event of a power failure. each block of memory can be located in a different address space as defined by the user. the access times for all memory types includes the address latching and dpld decoding time. 4.2 plds the device contains two pld blocks, each optimized for a different function, as shown in table 2. the functional partitioning of the plds reduces power consumption, optimizes cost/performance, and eases design entry. the decode pld (dpld) is used to decode addresses and generate chip selects for the psd935g2 internal memory and registers. the general purpose pld (gpld) can implement user-defined external chip selects and logic functions. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms. the plds consume minimal power by using zero-power design techniques. the speed and power consumption of the pld is controlled by the turbo bit in the pmmr0 register and other bits in the pmmr2 registers. these registers are set by the microcontroller at runtime. there is a slight penalty to pld propagation time when invoking the non-turbo bit. 4.3 i/o ports the psd935g2 has 52 i/o pins divided among seven ports (port a, b, c, d, e, f and g). each i/o pin can be individually configured for different functions. ports can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for microcontrollers using multiplexed address/data busses. the jtag pins can be enabled on port e for in-system programming (isp). ports f and g can also be configured as a data port for a non-multiplexed bus. 4.4 microcontroller bus interface the psd935g2 easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. the device is configured to respond to the microcontroller? control signals, which are also used as inputs to the plds. section 9.3.5 contains microcontroller interface examples. 4.0 psd9xx architectural overview name abbreviation inputs outputs product terms decode pld dpld 66 15 40 general pld gpld 66 24 136 table 2. pld i/o table
psd9xx architectural overview (cont.) 4.5 isp via jtag port in-system programming can be performed through the jtag pins on port e. this serial interface allows complete programming of the entire psd935g2 device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr, tdi, tdo) can be multiplexed with other functions on port e. table 3 indicates the jtag signals pin assignments. 4.6 in-system programming (isp) using the jtag signals on port e, the entire psd935g2 (memory, logic, configuration) device can be programmed or erased without the use of the microcontroller. port e pins jtag signal pe0 tms pe1 tck pe2 tdi pe3 tdo pe4 tstat pe5 terr table 3. jtag signals on port e psd9xx family psd935g2 6 4.7 in-application re-programming (iap) the main flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the secondary flash memory, or sram. since this is a sizable separate block, the application can also continue to operate. the secondary flash boot memory can be programmed the same way by executing out of the main flash memory. table 4 indicates which programming methods can program different functional blocks of the psd9xx. device functional block jtag-isp programmer iap main flash memory yes yes yes flash boot memory yes yes yes pld array (dpld and gpld) yes yes no psd configuration yes yes no table 4. methods of programming different functional blocks of the psd935g2 4.8 page register the eight-bit page register expands the address range of the microcontroller by up to 256 times.the paged address can be used as part of the address space to access external memory and peripherals or internal memory and i/o. the page register can also be used to change the address mapping of blocks of flash memory into different memory spaces for iap. 4.9 power management unit the power management unit (pmu) in the psd935g2 gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power down unit (apd) that will turn off device functions due to microcontroller inactivity. the apd unit has a power down mode that helps reduce power consumption. the psd935g2 also has some bits that are configured at run-time by the mcu to reduce power consumption of the gpld. the turbo bit in the pmmr0 register can be turned off and the gpld will latch its outputs and go to standby until the next transition on its inputs. additionally, bits in the pmmr2 register can be set by the mcu to block signals from entering the gpld to reduce power consumption. see section 9.5.
psd935g2 psd9xx family 7 merge mcu firmware with psd configuration st psd programmer *.obj file define psd pin and node functions point and click definition of psd pin functions, internal nodes, and mcu system memory map. choose mcu and psd automatically configures mcu bus interface and other psd attributes. psdpro or flashlink (jtag) a composite object file is created containing mcu firmware and psd configuration. c code generation generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj file available for 3rd party programmers (conventional or jtag-isp) mcu firmware hex or s-record format figure 2. psdsoft development tool 5.0 development system the psd9xx series is supported by psdsoft a windows-based (95, 98, nt) software development tool. a psd design is quickly and easily produced in a point and click environment. the designer does not need to enter hardware definition language (hdl) equations (unless desired) to define psd pin functions and memory map information. the general design flow is shown in figure 2 below. psdsoft is available from our web site (www .st .com /psm ) or other distribution channels. psdsoft directly supports two low cost device programmers from st. psdpro and flashlink (jtag). both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. the psd9xx is also supported by third party device programmers, see web site for current list.
psd9xx family psd935g2 8 the following table describes the pin names and pin functions of the psd935g2. pins that have multiple names and/or functions are defined using psd configuration. 6.0 table 5. psd935g2 pin descriptions pin* (tqfp pin name pkg.) type description adio0-7 3-7 i/o this is the lower address/data port. connect your mcu 10-12 address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad[0:7] to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a[0:7] to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. adio8-15 13-20 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect a[8:15] to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a[8:15] to this port. 3. if you are using an 80c251 in page mode, connect ad[8:15] to this port 4. if you are using an 80c51xa in burst mode, connect a[12:19] to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. cntl0 59 i the following control signals can be connected to this port, based on your mcu: 1. wr ?active-low write input. 2. r _ w ?active-high read/active low write input. this pin is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl1 60 i the following control signals can be connected to this port, based on your mcu: 1. rd ?active-low read input. 2. e ?e clock input. 3. ds ?active-low data strobe input. 4. psen ?connect psen to this port when it is being used as an active-low read signal. for example, when the 80c251 outputs more than 16 address bits, psen is actually the read signal. this pin is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl2 40 i this pin can be used to input the psen (program select enable) signal from any mcu that uses this signal for code exclusively. if your mcu does not output a program select enable signal, this port can be used as a generic input. this port is connected to the pld as input. reset 39 i active low input. resets i/o ports, pld micro ? cells, some of the configuration registers and jtag registers. must be active at power up. reset also aborts the flash programming/erase cycle that is in progress.
psd935g2 psd9xx family pin* (tqfp pin name pkg.) type description pa0-pa7 51-58 i/o port a, pa0-7. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port drain 2. gpld output. 3. input to the pld. pb0-pb7 61-68 i/o port b, pb0-7. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. gpld output. 3. input to the pld. pc0-pc7 41-48 i/o port c, pc0-7. this port is pin configurable and has multiple cmos functions: or slew 1. mcu i/o ?standard output or input port. rate 2. external chip select (ecs0-7) output. 3. input to the pld. pd0 79 i/o port d pin pd0 can be configured as: cmos 1. ale or as input ?latches addresses on adio0-15 pins or open 2. as input ?latches addresses on adio0-15 pins on the drain rising edge. 3. input to the pld. 4. transparent pld input. pd1 80 i/o port d pin pd1 can be configured as: cmos 1. mcu i/o or open 2. input to the pld. drain 3. clkin clock input ?clock input to the gpld micro ? cells, the apd power down counter and gpld and array. pd2 1 i/o port d pin pd2 can be configured as: cmos 1. mcu i/o or open 2. input to the pld. drain 3. csi input ?chip select input. when low, the csi enables the internal psd memories and i/o. when high, the internal memories are disabled to conserve power. csi trailing edge can get the part out of power-down mode. pd3 2 i/o port d pin pd3 can be configured as: cmos 1. mcu i/o or open 2. input to the pld. drain pe0 71 i/o port e, pe0. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. tms input for jtag/isp interface. pe1 72 i/o port e, pe1. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. tck input for jtag/isp interface (schmidt trigger). pe2 73 i/o port e, pe2. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. tdi input for jtag/isp interface. table 5. psd935g2 pin descriptions (cont.) 9
psd9xx family psd935g2 10 pin* (tqfp pin name pkg.) type description pe3 74 i/o port e, pe3. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. tdo output for jtag/isp interface. pe4 75 i/o port e, pe4. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. tstat output for the isp interface. 4. rdy/bsy ?for in-circuit parallel programming. pe5 76 i/o port e, pe5. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. terr active low output for isp interface. pe6 77 i/o port e, pe6. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. vstby ?sram standby voltage input for battery backup sram pe7 78 i/o port e, pe7. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address output. 3. vbaton ?battery backup indicator output. goes high when power is drawn from an external battery. pf0-pf7 31-38 i/o port f, pf0-7. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. input to the pld. 3. latched address outputs. 4. as address a0-3 inputs in 80c51xa mode 5. as data bus port (d0-7) in non-multiplexed bus configuration pg0-pg7 21-28 i/o port g, pg0-7. this port is pin configurable and has multiple cmos functions: or open 1. mcu i/o ?standard output or input port. drain 2. latched address outputs. gnd 8,30, 49,50, 70 v cc 9,29, 69 table 5. psd935g2 pin descriptions (cont.)
psd935g2 psd9xx family 11 table 6 shows the offset addresses to the psd935g2 registers relative to the csiop base address. the csiop space is the 256 bytes of address that is allocated by the user to the internal psd935g2 registers. table 6 provides brief descriptions of the registers in csiop space. for a more detailed description, refer to section 9. 7.0 psd935g2 register description and address offset register name port a port b port c port d port e port f port g other* description data in 00 01 10 11 30 40 41 reads port pin as input, mcu i/o input mode control 32 42 43 selects mode between mcu i/o or address out stores data for output data out 04 05 14 15 34 44 45 to port pins, mcu i/o output mode direction 06 07 16 17 36 46 47 configures port pin as input or output configures port pins as either cmos or open drive select 08 09 18 19 38 49 drain on some pins, while selecting high slew rate on other pins. flash protection c0 read only ?flash sector protection flash boot read only ?psd security protection c2 and flash boot sector protection pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register places psd memory vm e2 areas in program and/or data space on an individual basis. memory_id0 f0 read only ?flash and sram size memory_id1 f1 read only ?boot type and size table 6. register address offset
psd9xx family psd935g2 12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 data in registers ?port a, b, c, d, e, f and g 8.0 register bit definition all the registers in the psd935g2 are included here for reference. detail description of the registers are found in the functional block section of the data sheet. bit definitions: read only registers, read port pin status when port is in mcu i/o input mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 data out registers ?port a, b, c, d, e, f and g bit definitions: latched data for output to port pin when pin is configured in mcu i/o output mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 direction registers ?port a, b, c, d, e, f and g bit definitions: set register bit to 0 = configure corresponding port pin in input mode (default). set register bit to 1 = configure corresponding port pin in output mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 control registers ?ports e, f and g bit definitions: set register bit to 0 = configure corresponding port pin in mcu i/o mode (default). set register bit to 1 = configure corresponding port pin in latched address out mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 drive registers ?ports a, b, d, e, and g bit definitions: set register bit to 0 = configure corresponding port pin in cmos output driver (default). set register bit to 1 = configure corresponding port pin in open drain output driver. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 drive registers ?ports c and f bit definitions: set register bit to 0 = configure corresponding port pin as cmos output driver (default). set register bit to 1 = configure corresponding port pin in slew rate mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot flash protection register bit definitions: read only register sec_prot 1 = flash sector is write protected. sec_prot 0 = flash sector is not write protected.
psd935g2 psd9xx family 13 8.0 register bit definition (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_bit *** sec3_prot sec2_prot sec1_prot sec0_prot flash boot protection register bit definitions: sec_prot 1 = boot block sector is write protected. sec_prot 0 = boot block sector is not write protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pgr7 pgr6 pgr5 pgr4 pgr3 pgr2 pgr1 pgr0 page register bit definitions: configure page input to pld. default pgr[7:0] = 00. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ** pld pld pld * apd * mcells clk array-clk turbo enable pmmr0 register bit definitions: (default is 0) bit 1 0 = automatic power down (apd) is disabled. 1 = automatic power down (apd) is enabled. bit 3 0 = pld turbo is on. 1 = pld turbo is off, saving power. bit 4 0 = clkin input to the pld and array is connected. every clkin change will power up the pld when turbo bit is off. 1 = clkin input to pld and array is disconnected, saving power. bit 5 0 = clkin input to the pld micro ? cells is connected. 1 = clkin input to the pld micro ? cells is disconnected, saving power. * not used bit should be set to zero. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * pld pld pld pld pld * pld array dbe array ale array cntl2 array cntl1 array cntl0 array addr pmmr2 register bit definitions (defauld is 0): bit 0 0 = address a[7:0] are connected into the pld array. 1 = address a[7:0] are blocked from the pld array, saving power. note: in xa mode, a3-0 come from pf3-0 and a7-4 come from adio7-4. bit 2 0 = cntl0 input to the pld and array is connected. 1 = cntl0 input to the pld and array is disconnected, saving power. bit 3 0 = cntl1 input to the pld and array is connected. 1 = cntl1 input to the pld and array is disconnected, saving power. bit 4 0 = cntl2 input to the pld and array is connected. 1 = cntl2 input to the pld and array is disconnected, saving power. bit 5 0 = ale input to the pld and array is connected. 1 = ale input to the pld and array is disconnected, saving power. bit 6 0 = dbe input to the pld and array is connected. 1 = dbe input to the pld and array is disconnected, saving power. * not used bit should be set to zero.
psd9xx family psd935g2 14 8.0 register bit definition (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *** fl_data boot_data fl_code boot_code sr_code vm register bit definitions: bit 0 0 = psen can? access sram in 80c51xa modes. 1 = psen can access sram in 80c51xa modes. bit 1 0 = psen can? access boot in 80c51xa modes. 1 = psen can access boot in 80c51xa modes. bit 2 0 = psen can? access main flash in 80c51xa modes. 1 = psen can access main flash in 80c51xa modes. bit 3 0 = rd can? access boot in 80c51xa modes. 1 = rd can access boot in 80c51xa modes. bit 4 0 = rd can? access main flash in 80c51xa modes. 1 = rd can access main flash in 80c51xa modes. note: upon reset, bit1-bit4 are loaded to configurations selected by the user in psdsoft. bit 0 is always cleared by reset. bit 0 to bit 4 are active only when the device is configured in philips 80c51xa mode. not used bit should be set to zero. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s_size 3 s_size 2 s_size 1 s_size 0 f_size 3 f_size 2 f_size 1 f_size 0 memory_id0 register bit definitions: f_size[3:0] = 4h, main flash size is 2m bit. f_size[3:0] = 5h, main flash size is 8m bit. s_size[3:0] = 0h, sram size is 0k bit. s_size[3:0] = 1h, sram size is 16k bit. s_size[3:0] = 3h, sram size is 64k bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ** b_type 1 b_type 0 b_size 3 b_size 2 b_size 1 b_size 0 memory_id1 register bit definitions: b_size[3:0] = 0h, boot block size is 0k bit. b_size[3:0] = 2h, boot block size is 256k bit. b_type[1:0] = 0h, boot block is flash memory. * not used bit should be set to zero.
psd935g2 psd9xx family 15 9.0 the psd935g2 functional blocks as shown in figure 1, the psd935g2 consists of six major types of functional blocks: memory blocks pld blocks bus interface i/o ports power management unit jtag-isp interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. 9.1 memory blocks the psd935g2 has the following memory blocks: the main flash memory secondary flash memory sram. the memory select signals for these blocks originate from the decode pld (dpld) and are user-defined in psdsoft. table 7 summarizes which versions of the psd935g2 contain which memory blocks. main flash secondary flash device flash size sector size block size sector size sram psd935g2 512kb 64kb 32kb 8kb 8kb table 7. memory blocks 9.1.1 main flash and secondary flash memory description the main flash memory block is divided evenly into eight sectors. the secondary flash memory is divided into four sectors of eight kbytes each. each sector of either memory can be separately protected from program and erase operations. flash memory may be erased on a sector-by-sector basis and programmed word-by-word. flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. during a program or erase of flash, the status can be output on the rdy/bsy pin of port pe4. this pin is set up using psdsoft. 9.1.1.1 memory block selects the decode pld in the psd935g2 generates the chip selects for all the internal memory blocks (refer to the pld section). each of the eight flash memory sectors have a flash select signal (fs0-fs7) which can contain up to three product terms. each of the four secondary flash memory sectors have a select signal (csboot0-3) which can contain up to three product terms. having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. when using a microcontroller (80c51) with separate program and data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other before and after iap.
psd9xx family psd935g2 16 9.1.1.2 upper and lower block in main flash sector the psd935g2? main flash has eight 64k bytes sector. the 64k byte sector size may cause some difficulty in code mapping for an 8-bit mcu with only 64k byte address space. to resolve this mapping issue, the psd935g2 provides additional logic (figure 3) for the user to split the 8 sectors such that each sector has a lower and upper 32k byte block, and the two blocks can reside in different pages but in the same address range. if your design works with 64kb sectors, you don? need to configure this logic. if the design requires 32kb blocks in each sector, you need to define a ?a15?pld equation in psdsoft as the a15 address input to the main flash module. fa15 consists of 3 product terms and will control whether the mcu is accessing the lower or upper 32kb in the selected sector. below is an example for flash sector chip select fs0. a typical equation is fa15 = pgr4 of the page register. when pgr4 is 0 (page 00), the lower 32kb is selected. when pgr4 is switched to 1 by the user, the upper 32kb is selected. psdsoft will automatically generate the pld equations shown, based on your point and click selections. page = [pgr7...pgr0]; ?age register output ?ector chip select equation fs0 = ((0000h <= address <= 7fffh) & page = 00h) # ?elect first 32kb block ((0000h <= address <= 7fffh) & page = 10h); ?elect second 32kb block fa15 = pgr4; ?s address a15 input to the main flash if no fa15 equation is defined in psdsoft, the a15 that comes from the mcu address bus will be routed as input to the main flash instead of fa15. the fa15 equation has no impact in the sector erase operation. note: fa15 affects all eight sectors of the main flash simultaneously, you cannot direct fa15 to a particular flash sector only. 9.1.1.3 the ready/busy pin (pe4) pin pe4 can be used to output the ready/busy status of the psd935g2. the output on the pin will be a ??(busy) when flash memory blocks are being written to, or when the flash memory block is being erased. the output will be a ??(ready) when no write or erase operation is in progress. the psd935g2 functional blocks (cont.) dpld array fa15 a15 * set by psdsoft flash chip selects fs0-7 mux nvm control bit * main flash sector addr a15 a [14:0] figure 3. selecting the upper or lower block in a main flash sector
psd935g2 psd9xx family 9.1.1.4 memory operation the main flash and secondary flash memories are addressed through the microcontroller interface on the psd935g2 device. the microcontroller can access these memories in one of two ways: the microcontroller can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. the microcontroller can execute a specific instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash to invoke an embedded algorithm. these instructions are summarized in table 8. typically, flash memory can be read by the microcontroller using read operations, just as it would read a rom device. however, flash memory can only be erased and programmed with specific instructions. for example, the microcontroller cannot write a single byte directly to flash memory as one would write a byte to ram. to program a byte into flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. this status test is achieved by a read operation or polling the rdy/busy pin (pe4). the flash memory can also be read by using special instructions to retrieve particular flash device information (sector protect status and id). 9.1.1.4.1 instructions an instruction is defined as a sequence of specific operations. each received byte is sequentially decoded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. some instructions are structured to include read operations after the initial write operations. the sequencing of any instruction must be followed exactly. any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory will reset the device logic into a read array mode (flash memory reads like a rom device). the psd935g2 main flash and secondary flash support these instructions (see table 8): erase memory by chip or sector suspend or resume sector erase program a byte reset to read array mode read main flash identifier value read sector protection status bypass instruction these instructions are detailed in table 8. for efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cycle (unless the bypass instruction feature is used. see 9.1.1.7). address lines a15-a12 are don t care during the instruction write cycles. however, the appropriate sector select signal (fsi or csbooti) must be selected. the main flash and the secondary flash block have the same set of instructions (except read main flash id). the chip selects of the flash memory will determine which flash will receive and execute the instruction. the main flash is selected if any one of the fs0-7 is active, and the secondary flash block is selected if any one of the csboot0-3 is active. the psd935g2 functional blocks (cont.) 17
psd9xx family psd935g2 18 the psd935g2 functional blocks (cont.) fs0-7 or instruction csboot0-3 cycle 1 cycle 2 cycle 3 cycle 4 cycle5 cycle 6 cycle 7 read (note 5) 1 read ra rd read main flash id 1 aah 55h 90h read (notes 6,13) @555h @aaah @555h id @x01h read sector protection 1 aah 55h 90h read (notes 6,8,13) @555h @aaah @555h 00h or 01h @x02h program a flash byte 1 aah 55h a0h pd@pa @555h @aaah @555h erase one flash sector 1 aah 55h 80h aah 55h 30h 30h @555h @aaah @555h @555h @aaah @sa @next sa (note 7) erase flash block 1 aah 55h 80h aah 55h 10h (bulk erase) @555h @aaah @555h @555h @aaah @555h suspend sector erase 1 b0h (note 11) @xxxh resume sector erase 1 30h (note 12) @xxxh reset (note 6) 1 f0 @ any address unlock bypass 1 aah 55h 20h @555h @aaah @555h unlock bypass program 1 a0h pd@pa (note 9) @xxxh unlock bypass reset 1 90h 00h (note 10) @xxxh @xxxh table 9. instructions x = don t care. ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the wr# (cntl0) pulse. pd = data to be programmed at location pa. data is latched o the rising edge of wr# (cntl0) pulse. sa = address of the sector to be erased or verified. the chip select (fs0-7 or csboot0-3) of the sector to be erased must be active (high). notes: 1. all bus cycles are write bus cycle except the ones with the read label. 2. all values are in hexadecimal. 3. fs0-7 and csboot0-3 are active high and are defined in psdsoft. 4. only address bits a11-a0 are used in instruction decoding. a15-12 (or a16-a12) are don t care. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode after reading the flash id, sector protect status or if dq5 (error flag) goes high. 7. additional sectors to be erased must be entered within 80s. 8. the data is 00h for an unprotected sector and 01h for a protected sector. in the fourth cycle, the sector chip select is active and (a1 = 1, a0 = 0). 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program functions in non-erasing sectors, read the flash id or read the sector protect status, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase suspend mode. 13. the mcu cannot invoke these instructions while executing code from the same flash memory for which the instruction is intended. the mcu must fetch, for example, codes from the secondary block when reading the sector protection status of the main flash.
psd935g2 psd9xx family 19 the psd935g2 functional blocks (cont.) 9.1.1.5 power-up condition the psd935g2 internal logic is reset upon power-up to the read array mode. the fsi and csbooti select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal. any write cycle initiation is locked when v cc is below vlko. 9.1.1.6 read under typical conditions, the microcontroller may read the flash, or secondary flash memories using read operations just as it would a rom or ram device. alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. lastly, the microcontroller may use instructions to read special data from these memories. the following sections describe these read functions. 9.1.1.6.1 read the contents of memory main flash and secodary flash memories are placed in the read array mode after power-up, chip reset, or a reset flash instruction (see table 8). the microcontroller can read the memory contents of main flash or secondary flash by using read operations any time the read operation is not part of an instruction sequence. 9.1.1.6.2 read the main flash memory identifier the main flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 8). the psd935g2 main flash memory id is e8h. 9.1.1.6.3 read the flash memory sector protection status the flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 8). the read operation will produce 01h if the flash sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (main flash or secondary flash) can also be read by the microcontroller accessing the flash protection and flash boot protection registers in psd i/o space. see section 9.1.1.9.1 for register definitions. 9.1.1.6.4 read the erase/program status bits the psd935g2 provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of flash memory. these status bits minimize the time that the microcontroller spends performing these tasks and are defined in table 9. the status bits can be read as many times as needed. fsi/ csbooti dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 data toggle error erase flash v ih polling flag flag x time- x x x out table 9. status bits notes: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fsi/csbooti are active high. for flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see section 9.1.1.7 for details.
psd9xx family psd935g2 20 the psd935g2 functional blocks (cont.) 9.1.1.6.5 data polling flag dq7 when erasing or programming the flash memory bit dq7 outputs the complement of the bit being entered for programming/writing on dq7. once the program instruction or the write operation is completed, the true logic value is read on dq7 (in a read operation). flash memory specific features: data polling is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. during an erase instruction, dq7 outputs a 0 . after completion of the instruction, dq7 will output the last bit programmed (it is a 1 after erasing). if the location to be programmed is in a protected flash sector, the instruction is ignored. if all the flash sectors to be erased are protected, dq7 will be set to 0 for about 100 s, and then return to the previous addressed location. no erasure will be performed. 9.1.1.6.6 toggle flag dq6 the psd935g2 offers another way for determining when the flash memory program instruction is completed. during the internal write operation and when either the fsi or csbooti is true, the dq6 will toggle from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling will stop and the data read on the data bus d0-7 is the addressed memory location. the device is now accessible for a new read or write operation. the operation is finished when two successive reads yield the same output data. flash memory specific features: the toggle bit is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). if the location to be programmed belongs to a protected flash sector, the instruction is ignored. if all the flash sectors selected for erasure are protected, dq6 will toggle to 0 for about 100 s and then return to the previous addressed location. 9.1.1.6.7 error flag dq5 during a correct program or erase, the error bit will set to 0 . this bit is set to 1 when there is a failure during flash programming, sector erase, or bulk erase. in the case of flash programming, the error bit indicates the attempt to program a flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. the error bit may also indicate a timeout condition while attempting to program a byte. in case of an error in flash sector erase or byte program, the flash sector in which the error occurred or to which the programmed location belongs must no longer be used. other flash sectors may still be used. the error bit resets after the reset instruction. 9.1.1.6.8 erase time-out flag dq3 the erase timer bit reflects the time-out period allowed between two consecutive sector erase instructions. the erase timer bit is set to 0 after a sector erase instruction for a time period of 100 s + 20% unless an additional sector erase instruction is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 is set to 1 .
psd935g2 psd9xx family 21 9.1.1.7 programming flash memory flash memory must be erased prior to being programmed. the mcu may erase flash memory all at once or by-sector. flash memory sector erases to all logic ones (ff hex), and its bits are programmed to logic zeros. although erasing flash memory occurs on a sector basis, programming flash memory occurs on a word basis. the psd935g2 main flash and secondary flash memories require the mcu to send an instruction to program a word or perform an erase function (see table 8). once the mcu issues a flash memory program or erase instruction, it must check for the status of completion. the embedded algorithms that are invoked inside the psd935g2 support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or the ready/busy output pin. 9.1.1.7.1 data polling polling on dq7 is a method of checking whether a program or erase instruction is in progress or has completed. figure 4 shows the data polling algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd935g2 begins. the mcu then reads the location of the word to be programmed in flash to check status. data bit dq7 of this location becomes the compliment of data bit 7of the original data word to be programmed. the mcu continues to poll this location, comparing dq7 and monitoring the error bit on dq5. when the dq7 matches data bit 7 of the original data, and the error bit at dq5 remains 0 , then the embedded algorithm is complete. if the error bit at dq5 is 1 , the mcu should test dq7 again since dq7 may have changed simultaneously with dq5 (see figure 4). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the location or if the mcu attempted to program a 1 to a bit that was not erased (not erased is logic 0 ). it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to flash with the word that was intended to be written. when using the data polling method after an erase instruction, figure 4 still applies. however, dq7 will be 0 until the erase operation is complete. a 1 on dq5 will indicate a timeout failure of the erase operation, a 0 indicates no error. the mcu can read any location within the sector being erased to get dq7 and dq5. psdsoft generates ansi c code functions which implement these data polling algorithms. the psd935g2 functional blocks (cont.)
psd9xx family psd935g2 22 figure 4. data polling flow chart start read dq5 & dq7 at valid address yes yes yes no no no dq7 = data 7 dq5 =1 dq7 = data read dq7 fail program/erase operation failed issue reset instruction pass program/erase operation is completed the psd935g2 functional blocks (cont.) 9.1.1.7.2 data toggle checking the data toggle bit on dq6 is a method of determining whether a program or erase instruction is in progress or has completed. figure 5 shows the data toggle algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd935g2 begins. the mcu then reads the location to be programmed in flash to check status. data bit dq6 of this location will toggle each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this location, checking dq6 and monitoring the error bit on dq5. when dq6 stops toggling (two consecutive reads yield the same value), and the error bit on dq5 remains 0 , then the embedded algorithm is complete. if the error bit on dq5 is 1 , the mcu should test dq6 again, since dq6 may have changed simultaneously with dq5 (see figure 5). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program, or if the mcu attempted to program a 1 to a bit that was not erased (not erased is logic 0 ).
psd935g2 psd9xx family 23 9.1.1.7.2 data toggle (cont.) it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to flash with the word that was intended to be written. when using the data toggle method after an erase instructin, figure 5 still applies. dq6 will toggle until the erase operation is complete. a 1 on dq5 will indicate a timeout failure of the erase operation, a 0 indicates no error. the mcu can read any even location within the sector being erased to get dq6 and dq5. psdsoft generates ansi c code functions which implement these data toggling algorithms. the psd935g2 functional blocks (cont.) figure 5. data toggle flow chart start read dq5 & dq6 no yes no yes yes no dq6 = toggle dq5 =1 dq6 = toggle read dq6 fail program/erase operation failed issue reset instruction pass program/erase operation is completed
psd9xx family psd935g2 24 the psd935g2 functional blocks (cont.) 9.1.1.8 unlock bypass instruction the unlock bypass feature allows the system to program words to the flash memories faster than using the standard program instruction. the unlock bypass instruction is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h (see table 8). the flash memory then enters the unlock bypass mode. a two-cycle unlock bypass program instruction is all that is required to program in this mode. the first cycle in this instruction contains the unlock bypass programm command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program instruction, resulting in faster total programming time. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset instructions are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don t care for both cycles. the flash memory then returns to reading array data mode. 9.1.1.9 erasing flash memory 9.1.1.9.1. flash bulk erase instruction the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in table 8. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section 9.1.1.7. the error bit (dq5) returns a 1 if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the array with 00h because the psd935g2 will automatically do this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory will not accept any instructions. 9.1.1.9.2 flash sector erase instruction the sector erase instruction uses six write operations, as described in table 8. additional flash sector erase confirm commands and flash sector addresses can be written subsequently to erase other flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 s. the input of a new sector erase instruction will restart the time-out period. the status of the internal timer can be monitored through the level of dq3 (erase time-out bit). if dq3 is 0 , the sector erase instruction has been received and the timeout is counting. if dq3 is 1 , the timeout has expired and the psd935g2 is busy erasing the flash sector(s). before and during erase timeout, any instruction other than erase suspend and erase resume will abort the instruction and reset the device to read array mode. it is not necessary to program the flash sector with 00h as the psd935g2 will do this automatically before erasing. during a sector erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section 9.1.1.7. during execution of the erase instruction, the flash block logic accepts only reset and erase suspend instructions. erasure of one flash sector may be suspended, in order to read data from another flash sector, and then resumed.
psd935g2 psd9xx family 25 the psd935g2 functional blocks (cont.) 9.1.1.9.3 flash erase suspend instruction when a flash sector erase operation is in progress, the erase suspend instruction will suspend the operation by writing 0b0h to any even address when an appropriate chip select (fsi or csbooti) is true. (see table 8). this allows reading of data from another flash sector after the erase operation has been suspended. erase suspend is accepted only during the flash sector erase instruction execution and defaults to read array mode. an erase suspend instruction executed during an erase timeout will, in addition to suspending the erase, terminate the time out. the toggle bit dq6 stops toggling when the psd935g2 internal logic is suspended. the toggle bit status must be monitored at an address within the flash sector being erased. the toggle bit will stop toggling between 0.1 s and 15 s after the erase suspend instruction has been executed. the psd935g2 will then automatically be set to read flash block memory array mode. if an erase suspend instruction was executed, the following rules apply: attempting to read from a flash sector that was being erased will output invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and will only respond to erase resume and reset instructions (read is an operation and is ok). if a reset instruction is received, data in the flash sector that was being erased will be invalid. 9.1.1.9.4 flash erase resume instruction if an erase suspend instruction was previously executed, the erase operation may be resumed by this instruction. the erase resume instruction consists of writing 030h to any even address while an appropriate chip select (fsi or csbooti) is true. (see table 8.) 9.1.1.10 specific features 9.1.1.10.1 main flash and secondary flash sector protect each sector of main flash and secondary flash memory can be separately protected against program and erase functions. sector protection provides additional data security because it disables all program or erase operations. this mode can be activated (or deactivated) through the jtag-isp port or a device programmer. sector protection can be selected for each sector using the psdsoft program. this will automatically protect selected sectors when the device is programmed through the jtag port or a device programmer. flash sectors can be unprotected to allow updating of their contents using the jtag port or a device programmer. the microcontroller can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash sector will be ignored by the device. the verify operation will result in a read of the protected data. this allows a guarantee of the retention of the protection status. the sector protection status can either be read by the mcu through the flash protection and secondary flash protection registers (csiop) or use the read sector protection instruction (table 8).
psd9xx family psd935g2 26 the psd935g2 functional blocks (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot flash protection register 9.1.1.10.2 reset instruction the reset instruction consists of one write cycle (see table 8). it can also be optionally preceded by the standard two write decoding cycles (writing aah to aaah and 55h to 554h). the reset instruction must be executed after: 1. reading the flash protection status or flash id using the flash instruction. 2. when an error condition occurs (dq5 goes high) during a flash programming or erase cycle. the reset instruction will reset the flash to normal read mode immediately. however, if there is an error condition (dq5 goes high), the flash memory will return to the read mode in 25 seconds after the reset instruction is issued. the reset instruction is ignored when it is issued during a flash programming or bulk erase cycle. the reset instruction will abort the on going sector erase cycle and return the flash memory to normal read mode in 25 seconds. 9.1.1.10.3 reset pin input the reset pulse input from the pin will abort any operation in progress and reset the flash memory to read mode. when the reset occurs during a programming or erase cycle, the flash memory will take up to 25 seconds to return to read mode. it is recommended that the reset pulse (except power on reset, see reset section) be at least 25 seconds such that the flash memory will always be ready for the mcu to fetch the boot code after reset is over. bit definitions: sec_prot 1 = main flash sector is write protected. sec_prot 0 = main flash sector is not write protected. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_ *** sec3_prot sec2_prot sec1_prot sec0_prot bit flash boot protection register bit definitions: sec_prot 1 = flash boot sector is write protected. sec_prot 0 = flash boot sector is not write protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. table 10. sector protection/security bit definition *: not used.
psd935g2 psd9xx family 27 the psd935g2 functional blocks (cont.) 9.1.2 sram the sram is enabled when rs0 the sram chip select output from the dpld is high. rs0 can contain up to three product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to the vstby pin (pe6). if you have an external battery connected to the psd935g2, the contents of the sram will be retained in the event of a power loss. the contents of the sram will be retained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. pin pe7 can be configured as an output that indicates when power is being drawn from the external battery. this vbaton signal will be high with the supply voltage falls below the bat- tery voltage and the battery on pe6 is supplying power to the internal sram. the chip select signal (rs0) for the sram, vstby, and vbaton are all configured using psdsoft. 9.1.3 memory select signals the main flash (fsi), secondary flash (csbooti), and sram (rs0) memory select signals are all outputs of the dpld. they are defined using psdsoft. the following rules apply to the equations for the internal chip select signals: 1. main flash memory and secondary flash memory sector select signals must not be larger than the physical sector size. 2. any main flash memory sector must not be mapped in the same memory space as another main flash sector. 3. a secondary flash memory sector must not be mapped in the same memory space as another flash boot sector. 4. sram and i/o spaces must not overlap. 5. a secondary flash memory sector may overlap a main flash memory sector. in case of overlap, priority will be given to the flash boot sector. 6. sram and i/o spaces may overlap any other memory sector. priority will be given to the sram and i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 will always access the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) will automatically address boot memory segment 0. any address greater than 9fffh will access the flash memory segment 0. you can see that half of the flash memory segment 0 and one-fourth of boot segment 0 can not be accessed in this example. also note that an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 6 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest.
psd9xx family psd935g2 28 the psd935g2 functional blocks (cont.) level 1 sram, i /o level 2 secondary flash memory highest priority lowest priority level 3 main flash memory figure 6. priority level of memory and i/o components 9.1.3.1. memory select configuration for mcus with separate program and data spaces the 80c51 and compatible family of microcontrollers, can be configured to have separate address spaces for code memory (selected using psen) and data memory (selected using rd). any of the memories within the psd935g2 can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the psd s csiop space. the vm register is set using psdsoft to have an initial value. it can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and main flash in data space at boot, and secondary flash memory in program space at boot, and later swap main and secondary flash memory. this is easily done with the vm register by using psdsoft to configure it for boot up and having the microcontroller change it when desired. table 11 describes the vm register. bit 7 bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 pio_en fl_data boot_data fl_code boot_code sram_code 0 = disable ** 0 = rd 0 = rd 0 = psen 0 = psen 0 = psen pio mode can t can t can t can t can t access access access access access flash boot flash flash boot flash sram 1= enable ** 1 = rd 1 = rd 1 = psen 1 = psen 1 = psen pio mode access access access access access flash boot flash flash boot flash sram table 11. vm register note: bits 6-5 are not used.
psd935g2 psd9xx family 29 the psd935g2 functional blocks (cont.) main flash dpld flash boot block sram rs0 csboot0-3 fs0-7 cs cs cs oe oe rd psen oe figure 7. 80c51xa memory modes ?separate space mode main flash dpld flash boot block sram rs0 csboot0-3 fs0-7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe figure 8. 80c51xa memory mode ?combined space mode 9.1.3.2 configuration modes for mcus with separate program and data spaces 9.1.3.2.1 separate space modes code memory space is separated from data memory space. for example, the psen signal is used to access the program code from the main flash memory, while the rd signal is used to access data from the secondary flash memory, sram and i/o ports. this configuration requires the vm register to be set to 0ch. 9.1.3.2.2 . combined space modes the program and data memory spaces are combined into one space that allows the main flash memory, secondary flash memory, and sram to be accessed by either psen or rd. for example, to configure the main flash memory in combined space mode, bits 2 and 4 of the vm register are set to 1 . 9.1.3.3 80c51xa memory map example see application notes for examples.
psd9xx family psd935g2 30 reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and gpld internal selects and logic flash pld pgr4 pgr5 pgr6 pgr7 figure 9. page register the psd935g2 functional blocks (cont.) 9.1.4 page register the eight bit page register increases the addressing capability of the microcontroller by a factor of up to 256. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr7) are inputs to the pld decoder and can be included in the flash memory, secondary flash memory, and sram chip select equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the pld for general logic. see application notes. figure 9 shows the page register. the eight flip flops in the register are connected to the internal data bus d0-d7. the microcontroller can write to or read from the page register. the page register can be accessed at address location csiop + e0h.
psd935g2 psd9xx family 31 the psd935g2 functional blocks (cont.) 9.1.5 memory id registers the 8-bit read only memory status registers are included in the csiop space. the user can determine the memory configuration of the psd device by reading the memory id0 and memory id1 registers. the content of the registers are defined as follow: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s_size 3 s_size 2 s_size 1 s_size 0 f_size 3 f_size 2 f_size 1 f_size 0 memory_id0 register main flash size f_size3 f_size2 f_size1 f_size0 (bit) 0 0 0 0 none 0 0 0 1 256k 0 0 1 0 512k 0 0111m 0 1002m 0 1014m 0 1108m bit definition sram size s_size3 s_size2 s_size1 s_size0 (bit) 0 0 0 0 none 0 00116k 0 01032k 0 01164k bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ** b_type 1 b_type 0 b_size 3 b_size 2 b_size 1 b_size 0 memory_id1 register * not used bit should be set to zero. boot block size b_size3 b_size2 b_size1 b_size0 (bit) 0 0 0 0 none 0 0 0 1 128k 0 0 1 0 256k 0 0 1 1 512k bit definition b_type1 b_type0 boot block type 0 0 flash 0 1 eeprom
psd9xx family psd935g2 32 the psd935g2 functional blocks (cont.) 9.2 plds the plds bring programmable logic functionality to the psd935g2. after specifying the logic for the plds in psdsoft, the logic is programmed into the device and available upon power-up. the psd935g2 contains two plds: the decode pld (dpld), and the general purpose pld (gpld). the plds are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. figure 11 shows the configuration of the plds. the dpld performs address decoding for internal components, such as memory, registers, and i/o port selects. the gpld can be used to generate external chip selects, control signals or logic functions. the gpld has 24 outputs that are connected to port a, b and c. the and array is used to form product terms. these product terms are specified using psdsoft. an input bus consisting of 66 signals is connected to the plds. the signals are shown in table 12. the complement of the 66 signals are also available as inputs to the and array. input source input name number of signals mcu address bus a[15:0] * 16 mcu control signals cntl[2:0] 3 reset rst 1 power down pdn 1 port a input pa[7-0] 8 port b input pb[7-0] 8 port c input pc[7-0] 8 port d inputs pd[3:0] 4 port f inputs pf[7:0] 8 page register pgr(7:0) 8 flash programming status bit rdy/bsy 1 table 12. dpld and gpld inputs note: the address inputs are a[19:4] in 80c51xa mode. the turbo bit the plds in the psd935g2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. setting the turbo mode bit to off (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turbo-off mode increases propagation delays while reducing power consumption. refer to the power management unit section on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations.
psd935g2 psd9xx family 33 pld input bus 8 csiop select sram select flash boot memory selects decode pld page register gpld general purpose pld flash memory selects data bus 8 pld out port a port b port c pld out pld out port a pld input port b pld input port c pld input port d pld input port f pld input 4 1 1 fa15 1 8 8 8 8 4 8 8 8 66 66 port d port f figure 10. pld block diagram
psd9xx family psd935g2 34 the psd935g2 functional blocks (cont.) 9.2.1 decode pld (dpld) the dpld, shown in figure 11, is used for decoding the address for internal components. the dpld can generate the following decode signals: 8 sector selects for the main flash memory (three product terms each) 4 sector selects for the secondary flash memory (three product terms each) 1 internal sram select (three product terms) 1 internal csiop select (select psd registers, one product term) 1 main flash address input (fa15, three product terms). fa15 selects the lower or upper 32kb block in the main flash sector. see the memory blocks section for details. inputs to the dpld chip selects may include address inputs, page register inputs and other user defined external inputs from ports a, b, c, d or f. 9.2.2 general purpose pld (gpld) the general purpose pld implements user defined system combinatorial logic function or chip selects for external devices. figure 12 shows how the gpld is connected to the i/o ports. the gpld has 24 outputs and each are routed to a port pin. the port pin can also be configured as input to the gpld. when it is not used as gpld output or input, the pin can be configured to perform other i/o functions. all gpld outputs are identical except in the number of available product terms (pds) for logic implementation. select the pin that can best meet the pt requirement of your logic function or chip select. in general, a pt is consumed for each logic or function that you specify in psdsoft. however, certain logic functions can consume more than one pt even if no logic or is specified (such as specifying an address range with boundaries of high granularity). table 13 shows the number of native pts for each gpld output pin. a native pt means that a particular pt is dedicated to an output pin. for example, table 13 shows that psd port a pin pa0 has 3 native product terms. this means a guaranteed minimum of 3 pts is available to implement logic for that pin. psd silicon and psdsoft can include additional pts beyond the native pts to implement logic. this is a transparent operation that occurs as needed through pt expansion (internal feedback) or pt allocation (internal borrowing). you may notice in the fitter report generated by psdsoft that for a given gpld output pin, more pts were used to implement logic than the number of native pts available for that pin. this is because psdsoft has called on unused pts from other gpld output pins to make your logic design fit (pt allocation or pt expansion). for optimum results, choose a gpld output pin with a large number of native pts for complicated logic. gpld output on port pin number of native product terms port a, pins pa0-3 3 port a, pins pa4-7 9 port b, pins pb0-3 4 port b, pins pb4-7 7 port c, pins pc0-7 1 table 13: gpld product term availability
psd935g2 psd9xx family 35 (inputs) (32) (16) (1) pdn (apd output) i /o ports (port a,b,c,f) (8) pgr0 - pgr7 a [ 15:0 ] * (4) (3) pd [ 3:0 ] (ale,clkin,csi) cntrl [ 2:0 ] ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop 8 flash memory sector selects 4 secondary flash memory sector selects sram select i/o decoder select csboot 0 csboot 1 csboot 2 csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 3 fa15 main flash address input 3 figure 11. dpld logic array * notes: 1. the address inputs are a[19:4] in 80c51xa mode. 2. additional address lines can be brought into psd via port a, b, c, c or f.
psd9xx family psd935g2 36 product term pin pa0-3 has 3 native pts pin pa4-7 has 9 native pts polarity select other i/o function other i/o function other i/o function general purpose pld (gpld) i/o port pld input bus mux pld input pld input pld input and array port a product term pin pb0-3 has 4 native pts pin pb4-7 has 7 native pts polarity select pld output pld output mux and array port b product term pin pc0-7 has 1 native pt polarity select pld output mux and array port c * * * figure 12. the micro ? cell and i/o port
psd935g2 psd9xx family 37 the psd935g2 functional blocks (cont.) 9.3 microcontroller bus interface the no-glue logic psd935g2 microcontroller bus interface can be directly connected to most popular microcontrollers and their control signals. key 8-bit microcontrollers with their bus types and control signals are shown in table 14. the mcu interface type is specified using the psdsoft. 9.3.1. psd935g2 interface to a multiplexed bus figure 13 shows an example of a system using a microcontroller with a 8-bit multiplexed bus and a psd935g2. the adio port on the psd935g2 is connected directly to the microcontroller address/data bus. ale latches the address lines internally. latched addresses can be brought out to port e, f or g. the psd935g2 drives the adio data bus only when one of its internal resources is accessed and the rd input is active. should the system address bus exceed sixteen bits, ports a, b, c, or f may be used as additional address inputs. 9.3.2. psd935g2 interface to a non-multiplexed bus figure 14 shows an example of a system using a microcontroller with a 8-bit non-multiplexed bus and a psd935g2. the address bus is connected to the adio port, and the data bus is connected to port f. port f is in tri-state mode when the psd935g2 is not accessed by the microcontroller. should the system address bus exceed sixteen bits, ports a, b or c may be used for additional address inputs. data bus mcu width cntl0 cntl1 cntl2 pc7 pd0** adio0 pf3-pf0 pf7-pf4 8031/8051 8 wr rd psen * ale a0 ** 80c51xa 8 wr rd psen * ale a4 a3-a0 * 80c251 8 wr psen ** ale a0 ** 80c251 8 wr rd psen * ale a0 ** 80198 8 wr rd ** ale a0 ** 68hc11 8 r/w e ** as a0 ** 68hc05c0 8 wr rd ** as a0 ** 68hc912 8 r/w e * dbe as a0 ** z80 8 wr rd *** a0 d3-d0 d7-d4 z8 8 r/w ds ** as a0 ** 68330 8 r/w ds ** as a0 ** m37702m2 8 r/w e ** ale a0 d3-d0 d7-d4 table 14. microcontrollers and their control signals * * unused cntl2 pin can be configured as pld input. other unused pins (pd3-0, pa3-0) can be ** configured for other i/o functions. ** ale/as input is optional for microcontrollers with a non-multiplexed bus
psd9xx family psd935g2 38 the psd935g2 functional blocks (cont.) micro - controller wr rd bhe ale reset ad [ 7:0 ] a [ 15:8 ] a [ 15: 8 ] a [ 7: 0 ] adio port port f port g port a,b, or c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) a [ 23:16 ] ( optional ) ( optional ) psd935g2 figure 13. an example of a typical 8-bit multiplexed bus interface micro - controller wr rd bhe ale reset d [ 7:0 ] a [ 15:0 ] a [ 23:16 ] d [ 7:0 ] adio port port f port g port a,b or c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) psd935g2 figure 14. an example of a typical 8-bit non-multiplexed bus interface
psd935g2 psd9xx family 39 the psd935g2 functional blocks (cont.) 9.3.3 microcontroller interface examples figures 15 through 19 show examples of the basic connections between the psd935g2 and some popular microcontrollers. the psd935g2 control input pins are labeled as to the microcontroller function for which they are configured. the mcu interface is specified using the psdsoft. 9.3.3.1 80c31 figure 15 shows the interface to the 80c31, which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the microcontroller control signals psen, rd, and wr may be used for accessing the internal memory components and i/o ports. the ale input (pin pd0) latches the address. 9.3.3.2 80c251 the intel 80c251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in table 15. configuration 1 is 80c31 compatible, and the bus interface to the psd935g2 is identical to that shown in figure 15. configurations 2 and 3 have the same bus connection as shown in figure 16. there is only one read input (psen) connected to the cntl1 pin on the psd935g2. the a16 connection to the pa0 pin allows for a larger address input to the psd935g2. configuration 4 is shown in figure 17. the rd signal is connected to cntl1 and the psen signal is connected to the cntl2. the 80c251 has two major operating modes: page mode and non-page mode. in non-page mode, the data is multiplexed with the lower address byte, and ale is active in every bus cycle. in page mode, data d[7:0] is multiplexed with address a[15:8]. in a bus cycle where there is a page hit, the ale signal is not active and only addresses a[7:0] are changing. the psd935g2 supports both modes. in page mode, the psd bus timing is identical to non-page mode except the address hold time and setup time with respect to ale is not required. the psd access time is measured from address a[7:0] valid to data in valid.
psd9xx family psd935g2 40 the psd935g2 functional blocks (cont.) configuration 80c251 connecting to page mode read/write psd935g2 pins pins wr cntl0 non-page mode, 80c31 compatible 1 rd cntl1 a [ 7:0 ] multiplex with d [ 7:0 } psen cntl2 2 wr cntl0 non-page mode psen only cntl1 a [ 7:0 ] multiplex with d [ 7:0 } 3 wr cntl0 page mode psen only cntl1 a [ 15:8 ] multiplex with d [ 7:0 } 4 wr cntl0 page mode rd cntl1 a [ 15:8 ] multiplex with d [ 7:0 } psen cntl2 table 15. 80c251 configurations 9.3.3.3 80c51xa the philips 80c51xa microcontroller family supports an 8- or 16-bit multiplexed bus that can have burst cycles. address bits a[3:0] are not multiplexed, while a[19:4] are multiplexed with data bits d[15:0] in 16-bit mode. in 8-bit mode, a[11:4] are multiplexed with data bits d[7:0]. the 80c51xa can be configured to operate in eight-bit data mode. (shown in figure 18). the 80c51xa improves bus throughput and performance by executing burst cycles for code fetches. in burst mode, address a19-4 are latched internally by the psd935g2, while the 80c51xa changes the a3-0 lines to fetch up to 16 bytes of code. the psd access time is then measured from address a3-a0 valid to data in valid. the psd bus timing requirement in burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to ale does not apply. 9.3.3.4 68hc11 figure 19 shows an interface to a 68hc11 where the psd935g2 is configured in 8-bit multiplexed mode with e and r/w settings. the dpld can generate the read and wr signals for external devices.
psd935g2 psd9xx family 41 gnd 8 reset reset 30 49 50 70 v cc 92969 v cc v cc v cc gnd gnd gnd gnd a[15:8] a[15:8] ad[7:0] ad[7:0] 60 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 40 79 80 1 2 39 71 72 73 74 75 76 77 78 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (psen) pd0 (ale) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe2 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) reset reset wr rd psen ale p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 wr psen ale/p 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 16 29 30 x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rxd txd ea/vp 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 10 11 31 crystal 80c31 rd 17 figure 15. interfacing the psd935g2 with an 80c31
psd9xx family psd935g2 42 gnd 8 reset reset 30 49 50 70 v cc 9 a16 a17 29 69 v cc v cc v cc gnd gnd gnd gnd a[17:8] a[15:8] ad[7:0] ad[7:0] * ** 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (psen) pd0 (ale) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) reset reset wr rd a16 a17 ale p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 wr rd/a16 psen ale p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 x1 x2 p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 reset ea 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 10 35 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 18 19 32 33 crystal 80c251sb psd935g2 u1 figure 16. interfacing the psd935g2 to the 80c251, with one read input * *connection is optional. **non-page mode: ad[7:0] - adio[7:0].
psd935g2 psd9xx family 43 gnd 8 reset reset 30 49 50 70 v cc 92969 v cc v cc v cc gnd gnd gnd gnd ad[15:8] ad[15:8] a[7:0] a[7:0] ** 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (psen) pd0 (ale) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) reset reset wr rd ale p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 wr rd/a16 psen ale p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 x1 x2 p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 reset ea 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 10 35 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 18 32 33 crystal 80c251sb psd935g2 60 19 psen figure 17. interfacing the psd935g2 to the 80c251, with read and psen inputs
psd9xx family psd935g2 44 gnd 8 reset 30 49 50 70 v cc 92969 v cc v cc v cc gnd gnd gnd gnd a[19:12] d[7:0] a[3:0] 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a13 a14 a15 a16 a17 a18 a19 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (psen) pd0 (ale) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) reset wr reset rd a3 a2 a1 a0 v cc psen ale a0 a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 a3 a2 a1 a0/wrh wrl rd psen ale 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 5 4 3 2 18 19 32 33 xtal1 xtal2 rxd0 txd0 rxd1 txd1 t2ex t2 t0 rst int0 int1 ea/wait busw 21 20 11 13 6 7 9 8 16 10 14 15 35 17 crystal xa-g3 psd935g2 figure 18. interfacing the psd935g2 to the 80c51xa, 8-bit data bus
psd935g2 psd9xx family 45 gnd 8 reset 30 49 50 70 v cc 92969 v cc v cc v cc gnd gnd gnd gnd a[15:8] a[15:8] ad[7:0] ad[7:0] 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (r/w) cntl1 (e) cntl2 pd0 (as) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) reset reset rw e as pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 rw e as reset pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 xt ex irq xirq pd0 pd1 pd2 pd3 pd4 pd5 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl modb moda 34 33 32 31 30 29 28 27 8 7 19 18 20 21 22 23 24 25 43 45 47 49 44 46 48 50 52 51 2 3 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 6 5 4 17 crystal 68hc11e9 psd935g2 figure 19. interfacing the psd935g2 with a 68hc11
psd9xx family psd935g2 46 the psd935g2 functional blocks (cont.) 9.4 i/o ports there are seven programmable i/o ports: ports a, b, c, d, e, f and g. each of the ports is eight bits except port d, which is 4 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft or by the microcontroller writing to on-chip registers in the csiop address space. the topics discussed in this section are: general port architecture port operating modes port configuration registers port data registers individual port functionality. 9.4.1 general port architecture the general architecture of the i/o port is shown in figure 20. individual port architectures are shown in figures 21 through 23. in general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. exceptions will be noted. as shown in figure 20, the ports contain an output multiplexer whose selects are driven by the configuration bits in the control registers (ports e, f and g only) and psdsoft configuration. inputs to the multiplexer include the following: output data from the data out register latched address outputs gpld outputs (external chip selects) the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the pdb is connected to the internal data bus for feedback and can be read by the microcontroller. the data out and micro ? cell outputs, direction and control registers, and port pin input are all connected to the pdb. the contents of these registers can be altered by the microcontroller. the pdb feedback path allows the microcontroller to check the contents of the registers. 9.4.2 port operating modes the i/o ports have several modes of operation. some modes can be defined using psdsoft, some by the microcontroller writing to the registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the microcontroller can be done so dynamically at run-time. the pld i/o, data port, address input, and mcu reset modes are the only modes that must be defined before programming the device. all other modes can be changed by the microcontroller at run-time. table 16 summarizes which modes are available on each port. table 19 shows how and where the different modes are configured. each of the port operating modes are described in the following subsections.
psd935g2 psd9xx family 47 internal data bus data out reg. dq d g q dq dq wr wr wr address gpld outputs ale read mux p d b control reg. dir reg. pld input data in output select output mux port pin data out address figure 20. general i/o port architecture the psd935g2 functional blocks (cont.) port mode port a port b port c port d port e port f port g mcu i/o yes yes yes yes yes yes yes pld outputs yes yes yes no no no no pld inputs yes yes yes yes no yes no address out no no no no yes yes yes (a7-0) (a7-0) (a7-0) or (a15-8) address in yes yes yes yes no yes no data port no no no no no yes no jtag isp no no no no yes no no table 16. port operating modes
psd9xx family psd935g2 48 control direction vm defined in register register register mode psdsoft setting setting setting declare 0 1 = output, mcu i/o pins only (note 1) 0 = input na declare pins pld i/o and logic or chip na na select equations data port selected for (port f) mcu with na na na non-mux bus address out declare 11na (port e, f, g) pins only address in declare pins (port a,b,c,d,f) na na na jtag isp declare pins na na na only table 17. port operating mode settings * na = not applicable note: 1. control register setting is not applicable to ports a, b and c. 9.4.2.1 mcu i/o mode in the mcu i/o mode, the microcontroller uses the psd935g2 ports to expand its own i/o ports. by setting up the csiop space, the ports on the psd935g2 are mapped into the microcontroller address space. the addresses of the ports are listed in table 6. a port pin can be put into mcu i/o mode by writing a ??to the corresponding bit in the control register (port e, f and g). the mcu i/o direction may be changed by writing to the corresponding bit in the direction register. see the subsection on the direction register in the ?ort registers?section. when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the microcontroller can read the port input through the data in buffer. see figure 20. ports a, b and c do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if they are specified in psdsoft. 9.4.2.2 pld i/o mode the pld i/o mode uses a port as an input to the cpld? input micro ? cells, and/or as an output from the gpld. the corresponding bit in the direction register must not be set to ??if the pin is defined as a pld input pin in psdsoft. the pld i/o mode is specified in psdsoft by declaring the port pins, and then specifying an equation in psdsoft. the psd935g2 functional blocks (cont.)
psd935g2 psd9xx family 49 the psd935g2 functional blocks (cont.) 9.4.2.4 address in mode for microcontrollers that have more than 16 address lines, the higher addresses can be connected to ports a, b, c, d or f and are routed as inputs to the plds. the address input can be latched by the address strobe (ale/as). any input that is included in the dpld equations for the main flash, boot flash, or sram is considered to be an address input. 9.4.2.5 data port mode port f can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port f if the port is configured as data port. data port mode is automatically configured in psdsoft when a non-multiplexed bus mcu is selected. 9.4.2.3 address out mode for microcontrollers with a multiplexed address/data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a ??for pins to use address out mode. this must be done by the mcu at run-time. see table 18 for the address output pin assignments on ports e, f and f for various mcus. note: do not drive address lines with address out mode to an external memory device if it is intended for the mcu to boot from the external device. the mcu must first boot from psd memory so the direction and control register bits can be set. mcu port e (3:0) port e (7:4) port f (3:0) port f (7:4) port g (3:0) port g (7:4) 80c51xa n/a * addr (7:4) n/a * addr (7:4) addr (11:8) n/a 80c251 n/a n/a n/a n/a addr (11:8) addr (15:12) (page mode) all other eight-bit addr (3:0) addr (7:4) addr (3:0) addr (7:4) addr (3:0) addr (7:4) multiplexed 8-bit non-mux n/a n/a n/a n/a addr (3:0) addr (7:4) bus table 18. i/o port latched address output assignments
psd9xx family psd935g2 50 9.4.3 port configuration registers (pcrs) each port has a set of pcrs used for configuration. the contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in table 6. the addresses in table 6 are the offsets in hex from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three pcrs, shown in table 19, are used for setting the port configurations. the default power-up state for each register in table 22 is 00h. register name port mcu access control e,f,g write/read direction a,b,c,d,e,f,g write/read drive select* a,b,c,d,e,f,g write/read table 19. port configuration registers * note: see table 22 for drive register bit definition. the psd935g2 functional blocks (cont.) 9.4.3.1 control register any bit set to ??in the control register sets the corresponding port pin to mcu i/o mode, and a ??sets it to address out mode. the default mode is mcu i/o. only ports e, f and g have an associated control register. 9.4.3.2 direction register the direction register controls the direction of data flow in the i/o ports. any bit set to ?? in the direction register will cause the corresponding pin to be an output, and any bit set to ??will cause it to be an input. the default mode for all port pins is input. figures 21 and 23 show the port architecture diagrams for ports a/b/c and e/f/g respectively. the direction of data flow for ports a, b, c and f are controlled by the direction register. an example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in table 21. since port d only contains four pins, the direction register for port d has only the four least significant bits active. direction register bit port pin mode 0 input 1 output table 20. port pin direction control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0000 111 table 21. port direction assignment example
psd935g2 psd9xx family drive bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register port a open open open open open open open open drain drain drain drain drain drain drain drain port b open open open open open open open open drain drain drain drain drain drain drain drain port c slew slew slew slew slew slew slew slew rate rate rate rate rate rate rate rate port d open open open open drain drain drain drain port e open open open open open open open open drain drain drain drain drain drain drain drain port g open open open open open open open open drain drain drain drain drain drain drain drain table 22. drive register pin assignment the psd935g2 functional blocks (cont.) 9.4.3.3 drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corresponding bit in the drive select register is set to a ?? the default pin drive is cmos. aside: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive register is set to ?? the default rate is slow slew. table 22 shows the drive register for ports a, b, c, d, e and g. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. port f always has cmos drive. 51 9.4.4 port data registers the port data registers, shown in table 23, are used by the microcontroller to write data to or read data from the ports. table 23 shows the register name, the ports having each register type, and microcontroller access for each register type. the registers are described below. 9.4.4.1 data in port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin input is read through the data in buffer. 9.4.4.2 data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to ?? the contents of the register can also be read back by the microcontroller. register name port mcu access data in a,b,c,d,e,f,g read ?input on pin data out a,b,c,d,e,f,g write/read table 23. port data registers
psd9xx family psd935g2 52 the psd935g2 functional blocks (cont.) 9.4.5 ports a, b and c ? functionality and structure ports a and b have similar functionality and structure, as shown in figure 21. the two ports can be configured to perform one or more of the following functions: mcu i/o mode gpld output combinatorial pld outputs. pld input input to the plds. address in ? additional high address inputs may be latched by ale. open drain/slew rate pins pc[7:0]can be configured to fast slew rate, pins pa[7:0] and pb[7:0] can be configured to open drain mode. internal data bus data out reg. dq dq wr wr read mux gpld output p d b pld input dir reg. data in output select output mux port pin data out figure 21 port a, b and c
psd935g2 psd9xx family 53 the psd935g2 functional blocks (cont.) 9.4.6 port d ? functionality and structure port d has four i/o pins. see figure 22. port d can be configured to program one or more of the following functions: mcu i/o mode pld input ? direct input to pld port d pins can be configured in psdsoft as input pins for other dedicated functions: pd0 ? ale, as address strobe input pd1 ? clkin, as clock input to the pld and apd counter pd2 ? csi, as active low chip select input. a high input will disable the flash/sram and csiop. pd3 ? dbe input from 68hc912 9.4.7 port e ? functionality and structure port e can be configured to perform one or more of the following functions (see figure 23): mcu i/o mode in-system programming ? jtag port can be enabled for programming/erase of the psd935g2 device. (see section 9.6 for more information on jtag programming.) pins that are configured as jtag pins in psdsoft will not be available for other i/o functions. open drain ? port e pins can be configured in open drain mode battery backup features pe6 can be configured as a battery input (vstby) pin. pe7 can be configured as a battery on indicator output pin, indicating when vcc is less than vbat. latched address output provided latched address (a7-0) output internal data bus data out reg. dq dq wr wr read mux p d b pld input dir reg. data in output select output mux port d pin data out figure 22. port d structure
psd9xx family psd935g2 54 the psd935g2 functional blocks (cont.) internal data bus data out reg. dq d g q dq dq wr wr wr address ale read mux p d b control reg. dir reg. pld input (port f) isp or battery back-up (port e) data in output select output mux port pin data out address a [ 7:0 ] or a [ 15:8 ] configuration bit figure 23. ports e, f and g structure 9.4.8 port f ? functionality and structure port f can be configured to perform one or more of the following functions: mcu i/o mode pld input ? as direct input ot the pld array. address in ? additional high address inputs. direct input to the pld array. latched address out ? provide latched address out per table 18. slew rate ? pins can be set up for fast slew rate. data port ? connected to d[7:0] when port f is configured as data port for a non-multiplexed bus. 9.4.9 port g ? functionality and structure port g can be configured to perform one or more of the following functions: mcu i/o mode latched address out ? provide latched address out per table 18. open drain ? pins can be configured in open drain mode
psd935g2 psd9xx family 55 9.5 power management the psd935g2 offers configurable power saving options. these options may be used individually or in combinations, as follows: all memory types in a psd (flash, secondary flash, and sram) are built with zero-power technology. in addition to using special silicon design methodology, zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ?akes up? changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingit happens automatically. the pld sections can also achieve standby mode when its inputs are not changing, see pmmr registers below. like the zero-power feature, the automatic power down (apd) logic allows the psd to reduce to standby current automatically. the apd will block mcu address/data signals from reaching the memories and plds. this feature is available on all psd935g2 devices. the apd unit is described in more detail in section 9.5.1. built in logic will monitor the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd logic initiates power down mode (if enabled). once in power down mode, all address/data signals are blocked from reaching psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of standby mode, but not the memories. the psd chip select input (csi) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd logic, especially if your mcu has a chip select output. there is a slight penalty in memory access time when the csi signal makes its initial transition from deselected to selected. the pmmr registers can be written by the mcu at run-time to manage power. all psd devices support ?locking bits?in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figures 27 and 27a). significant power savings can be achieved by blocking signals that are not used in pld logic equations at run time. psdsoft creates a fuse map that automatically blocks the low address byte (a7-a0) or the control signals (cntl0-2, ale and wrh/dbe) if none of these signals are used in pld logic equations. the psd935g2 devices have a turbo bit in the pmmr0 register. this bit can be set to disable the turbo mode feature (default is turbo mode on). while turbo mode is disabled, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is enabled. conversely, when the turbo mode is enabled, there is a significant dc current component and the ac component is higher. 9.5.1 automatic power down (apd) unit and power down mode the apd unit, shown in figure 24, puts the psd into power down mode by monitoring the activity of the address strobe (ale/as). if the apd unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. if the address strobe remains inactive for fifteen clock periods of the clkin signal, the power down (pdn) signal becomes active, and the psd will enter into power down mode, discussed next. the psd935g2 functional blocks (cont.)
psd9xx family psd935g2 56 the psd935g2 functional blocks (cont.) access 5v v cc , pld memory recovery time typical propagation access to normal standby mode delay time access current power down normal tpd no access tlvdv 50 a (note 1) (note 2) table 25. psd935g2 timing and standby current during power down mode notes: 1. power down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption assuming no pld inputs are changing state and the pld turbo bit is off. port function pin level mcu i/o no change pld out no change address out undefined data port three-state peripheral i/o three-state table 24. power down modes effect on ports 9.5.1 automatic power down (apd) unit and power down mode (cont.) power down mode by default, if you enable the psd apd unit, power down mode is automatically enabled. the device will enter power down mode if the address strobe (ale/as) remains inactive for fifteen clkin (pin pd1) clock periods. the following should be kept in mind when the psd is in power down mode: if the address strobe starts pulsing again, the psd will return to normal operation. the psd will also return to normal operation if either the csi input returns low or the reset input returns high. the mcu address/data bus is blocked from all memories and plds. various signals can be blocked (prior to power down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clock (clkin). note that blocking clkin from the plds will not block clkin from the apd unit. all psd memories enter standby mode and are drawing standby current. however, the plds and i/o ports do not go into standby mode because you don? want to have to wait for the logic and i/o to ?ake-up?before their outputs can change. see table 24 for power down mode effects on psd ports. typical standby current is 50 a for 5 v parts. this standby current value assumes that there are no transitions on any pld input.
psd935g2 psd9xx family 57 apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface secondary flash select main flash select sram select pd clr pd disable main and secondary flash/sram pld select figure 24. apd logic block the psd935g2 functional blocks (cont.) enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bit 4 and pmmr2 bits 0. figure 25. enable power down flow chart
psd9xx family psd935g2 58 bit 1 0 = automatic power down (apd) is disabled. 1 = automatic power down (apd) is enabled. bit 3 0 = pld turbo is on. 1 = pld turbo is off, saving power. bit 4 0 = clkin input to the pld and array is connected. every clkin change will power up the pld when turbo bit is off. 1 = clkin input to pld and array is disconnected, saving power. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *** pld pld * apd * array clk turbo enable 1 = off 1 = off 1 = on table 26. power management mode registers (pmmr0, pmmr2)** pmmr0 ** * bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1. * ** the pmmr0, and pmmr2 register bits are cleared to zero following power up. *** subsequent reset pulses will not clear the registers. the psd935g2 functional blocks (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * pld pld pld ** pld ** pld ** * pld array array array array array array dbe ale cntl2 cntl1 cntl0 addr. 1 = off 1 = off 1 = off 1 = off 1 = off 1 = off pmmr2 bit 0 0 = address a[7:0] inputs to the pld and array are connected. 1 = address a[7:0] inputs to the pld and array are disconnected, saving power. note: in 80c51xa mode, a[7:1] comes from port f (pf1-pf3) and ad10 [3:0]. bit 2 0 = cntl0 input to the pld and array is connected. 1 = cntl0 input to pld and array is disconnected, saving power. bit 3 0 = cntl1 input to the pld and array is connected. 1 = cntl1 input to pld and array is disconnected, saving power. bit 4 0 = cntl2 input to the pld and array is connected. 1 = cntl2 input to pld and array is disconnected, saving power. bit 5 0 = ale input to the pld and array is connected. 1 = ale input to pld and array is disconnected, saving power. bit 6 0 = dbe input to the pld and array is connected. 1 = dbe input to pld and array is disconnected, saving power. * * unused bits should be set to 0. ** refer to table 14 the signals that are blocked on pins cntl0-2.
psd935g2 psd9xx family 59 apd ale enable bit pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks) table 27. apd counter operation the psd935g2 functional blocks (cont.) 9.5.2 other power saving options the psd935g2 offers other reduced power saving options that are independent of the power down mode. except for the sram standby and csi input features, they are enabled by setting bits in the pmmr0 and pmmr2 registers. 9.5.2.1 zero power pld the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to ?? the turbo mode is disabled and the plds consume zero power current when the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increased after the turbo bit is set to ??(turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is set to a ? (turned on), the plds run at full power and speed. the turbo bit affects the pld? d.c. power, ac power, and propagation delay. refer to ac/dc spec for pld timings. note: blocking mcu control signals with pmmr2 bits can further reduce pld ac power consumption. 9.5.2.2 sram standby mode (battery backup) the psd935g2 supports a battery backup operation that retains the contents of the sram in the event of a power loss. the sram has a vstby pin (pe6) that can be connected to an external battery. when v cc becomes lower than vstby then the psd will automatically connect to vstby as a power source to the sram. the sram standby current (istby) is typically 0.5 a. the sram data retention voltage is 2 v minimum. the battery-on indicator (vbaton) can be routed to pe7. this signal indicates when the v cc has dropped below the vstby voltage and that the sram is running on battery power. 9.5.2.3 the csi input pin pd2 of port d can be configured in psdsoft as the csi input. when low, the signal selects and enables the internal flash, boot block, sram, and i/o for read or write operations involving the psd935g2. a high on the csi pin will disable the flash memory, boot block, and sram, and reduce the psd power consumption. however, the pld and i/o pins remain operational when csi is high. note: there may be a timing penalty when using the csi pin depending on the speed grade of the psd that you are using. see the timing parameter t slqv in the ac/dc specs. 9.5.2.4 input clock the psd935g2 provides the option to turn off the clkin input to the pld and array to save ac power consumption. during power down mode, or, if the clkin input is not being used as part of the pld logic equation, the clock should be disabled to save ac power. the clkin will be disconnected from the pld and array by setting bit 4 to a ?? in pmmr0. 9.5.2.5 mcu control signals the psd935g2 provides the option to turn off the address input (a7-0) and input control signals (cntl0-2, ale, and dbe) to the pld to save ac power consumption. these signals are inputs to the pld and array. during power down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they will be disconnected from the pld and array by setting bits 0, 2, 3, 4, 5, and 6 to a ??in the pmmr2.
psd9xx family psd935g2 60 the psd935g2 functional blocks (cont.) 9.5.3 reset and power on requirement 9.5.3.1 power on reset upon power up the psd935g2 requires a reset pulse of tnlnh-po (minimum 1 ms) after v cc is steady. during this time period the device loads internal configurations, clears some of the registers and sets the flash into operating mode. after the rising edge of reset, the psd935g2 remains in the reset state for an additional topr (maximum 120 ns) nanoseconds before the first memory access is allowed. the psd935g2 flash memory is reset to the read array mode upon power up. the fsi and csbooti select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal. any flash memory write cycle initiation is prevented automatically when v cc is below vlko. 9.5.3.2 warm reset once the device is up and running, the device can be reset with a much shorter pulse of tnlnh (minimum 150 ns). the same topr time is needed before the device is operational after warm reset. figure 26 shows the timing of the power on and warm reset. operating level power on reset v cc reset t nlnh po t opr t nlnh-a t nlnh t opr warm reset figure 26. power on and warm reset timing 9.5.3.3 i/o pin, register and pld status at reset table 28 shows the i/o pin, register and pld status during power on reset, warm reset and power down mode. pld outputs are always valid during warm reset, and they are valid in power on reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are determined by the equations specified in psdsoft.
9.5.3.4 reset of flash erase and programming cycles an external reset on the reset pin will also reset the internal flash memory state machine. when the flash is in programming or erase mode, the reset pin will terminate the programming or erase operation and return the flash back to read mode in tnlnh-a (minimum 25 s) time. 9.6 programming in-circuit using the jtag-isp interface the jtag-isp interface on the psd935g2 can be enabled on port e (see table 29). all memory (flash and flash boot block), pld logic, and psd configuration bits may be programmed through the jtag-isc interface. a blank part can be mounted on a printed circuit board and programmed using jtag-isp. the standard jtag signals (ieee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr, are optional jtag extensions used to speed up program and erase operations. psd935g2 psd9xx family 61 port e pin jtag signals description pe0 tms mode select pe1 tck clock pe2 tdi serial data in pe3 tdo serial data out pe4 tstat status pe5 terr error flag table 29. jtag port signals the psd935g2 functional blocks (cont.) * sr_cod bit in the vm register are always cleared to zero on power on or warm reset. port configuration power on reset warm reset power down mode mcu i/o input mode input mode unchanged pld output valid after internal valid depend on inputs to psd configuration pld (address are bits are loaded blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated table 28. status during power on reset, warm reset and power down mode register power on reset warm reset power down mode pmmr0, 2 cleared to 0 ? unchanged unchanged vm register* initialized based on initialized based on unchanged the selection in the selection in psdsoft psdsoft configuration menu. configuration menu. all other registers cleared to 0 ? cleared to 0 ? unchanged by default, on a blank psd (as shipped from factory or after erasure), four pins on port e are enabled for the basic jtag signals tms, tck, tdi, and tdo. see st application note an1153 for more details on jtag in-system-programming.
psd9xx family psd935g2 62 9.6.1 standard jtag signals the jtag configuration bit (non-volatile) inside the psd can be set by the user in the psdsoft. once this bit is set and programmed in the psd, the jtag pins are dedicated to jtag at all times and is in compliance with ieee 1149.1. after power up the standard jtag signals (tdi, tdo tck and tms) are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is received from the external jtag controller, tdo becomes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally enable the two additional jtag pins, tstat and terr. the psd935g2 supports jtag isp commands, but not boundary scan. st s psdsoft software tool and flashlink jtag programming cable implement these jtag-isp commands. 9.6.2 jtag extensions tstat and terr are two jtag extension signals enabled by a jtag command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed programming and erase functions by indicating status on psd pins instead of having to scan the status out serially using the standard jtag channel. see application note 54. terr will indicate if an error has occurred when erasing a sector or programming a byte in flash memory. this signal will go low (active) when an error condition occurs, and stay low until a special jtag command is executed or a chip reset pulse is received after an isc-disable command. tstat behaves the same as the rdy/bsy signal described in section 9.1.1.3. tstat will be high when the psd935g2 device is in read array mode (flash memory and boot block contents can be read). tstat will be low when flash memory programming or erase cycles are in progress, and also when data is being written to the secondary flash block. tstat and terr can be configured as open-drain type signals with a jtag command. 9.6.3 security and flash memories protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program/erase/verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft. all flash memory and boot sectors can individually be sector protected against erasures. the sector protect bits can be set in psdsoft. the psd935g2 functional blocks (cont.)
psd935g2 psd9xx family range temperature v cc tolerance commercial 0 c to +70 c + 5 v 10% industrial 40 c to +85 c + 5 v 10% commercial 0 c to +70 c 3.0 v to 3.6 v industrial 40 c to +85 c 3.0 v to 3.6 v symbol parameter condition min max unit t stg storage temperature pldcc 65 + 125 c commercial 0 + 70 c operating temperature industrial 40 + 85 c voltage on any pin with respect to gnd 0.6 + 7 v v pp device programmer supply voltage with respect to gnd 0.6 + 14 v v cc supply voltage with respect to gnd 0.6 + 7 v esd protection > 2000 v 10.0 absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v cc supply voltage v-versions all speeds 3.0 3.6 v 12.0 recommended operating conditions 11.0 operating range 63
psd9xx family psd935g2 beta information 64 ac/dc parameters the following tables describe the ad/dc parameters of the psd9xx family: dc electrical specification ac timing specification pld timing combinatorial timing microcontroller timing read timing write timing power down and reset timing following are issues concerning the parameters presented: in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd9xx is in each mode. also, the supply power is considerably different if the turbo bit is "off". the ac power component gives the pld, flash memory, and sram ma/mhz specification. figures 27 and 27a show the pld ma/mhz as a function of the number of product terms (pt) used. in the pld timing parameters, add the required delay when turbo bit is "off". figure 27. pld i cc /frequencyconsumption (v cc = 5 v 10%) 0 10 20 30 40 60 70 80 90 100 110 v cc = 5v 50 01015 5 20 25 highest composite frequency at pld inputs (mhz) i cc ?(ma) turbo on (100%) turbo on (25%) turbo off turbo off pt 100% pt 25%
psd935g2 psd9xx family 65 figure 27a. pld i cc /frequency consumption (psd935g2v versions, v cc = 3 v) 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc ?(ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/176 = 25.5% turbo mode = on calculation (typical numbers used) i cc total = ipwrdown x %pwrdown + %normal x ( i cc (ac) + i cc (dc) ) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x 2 ma/mhz x freq pld + #pt x 400 a/pt = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz +2 ma/mhz x 8 mhz + 45 x 0.4 ma/pt) = 45 a + 0.1 x (8 + 0.9 + 16 + 18 ma) = 45 a + 0.1 x 42.9 = 45 a + 4.29 ma = 4.34 ma this is the operating power with no flash writes or erases. calculation is based on i out = 0 ma. example of psd935g2 typical power calculation at v cc = 5.0 v ac/dc parameters (cont.)
psd9xx family psd935g2 66 conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/176 = 25.5% turbo mode = off calculation (typical numbers used) i cc total = ipwrdown x %pwrdown + %normal x ( i cc (ac) + i cc (dc) ) = ipwrdown x %pwrdown + % normal x ( %flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld) ) = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 24 ma) = 45 a + 0.1 x (8 + 0.9 + 24) = 45 a + 0.1 x 32.9 = 45 a + 3.29 ma = 3.34 ma this is the operating power with no flash writes or erases. calculation is based on i out = 0 ma. example of typical power calculation at v cc = 5.0 v in turbo off mode ac/dc parameters (cont.)
psd935g2 psd9xx family 67 note: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal power down mode is active. 3. pld is in non-turbo mode and none of the inputs are switching 4. refer to figure 32 for pld current calculation. 5. i o = 0 ma symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v .5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v lko v cc min for flash erase and program 2.5 4.2 v v ol output low voltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.25 0.45 v v oh output high voltage except v stby on i oh = 20 a, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v oh 1 output high voltage v stby on i oh 1 = 1 a v sby ?0.8 v v sby sram standby voltage 2.0 v cc v i sby sram standby current (v stby pin) v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb standby supply current for power csi > v cc ?.3 v 100 200 a down mode (notes 2, 3 and 5) i li input leakage current v ss < v in < v cc ? .1 1 a i lo output leakage current 0.45 < v in < v cc ?0 5 10 a i o output current refer to i ol and i oh in the v ol and v oh row pld_turbo = off, 0ma f = 0 mhz (note 3) pld only pld_turbo = on, f = 0 mhz 400 700 a/pt i cc (dc) operating supply during flash write/erase (note 5) current flash only 15 30 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma pld ac base fig. 27 i cc (ac) (note 4) (note 5) flash ac adder 2.5 3.5 ma/mhz sram ac adder 1.5 3.0 ma/mhz psd935g2 dc characteristics (5 v 10% versions)
psd9xx family psd935g2 68 ac symbols for pld timing. example: t avlx ? time from address valid to ale invalid. signal letters a address input c ceout output d input data e e input i interrupt input l ale input n reset input or output p port signal output r uds, lds, ds, rd, psen inputs s chip select input t r/w input w wr input b vstby output m output micro ? cell signal behavior t time l logic level low or ale h logic level high v valid x no longer a valid logic level z float pw pulse width microcontroller interface ac/dc parameters (5v 10% versions)
-70 -90 turbo symbol parameter conditions min max min max off unit t lvlx ale or as pulse width 15 20 ns t avlx address setup time (note 3) 4 6 ns t lxax address hold time (note 3) 7 8 ns t avqv address valid to data valid (note 3) 70 90 add 12 ns t slqv cs valid to data valid 75 100 ns rd to data valid (note 5) 24 32 ns t rlqv rd or psen to data valid, 80c51 mode (note 2) 31 38 ns t rhqx rd data hold time (note 1) 0 0 ns t rlrh rd pulse width (note 1) 27 32 ns t rhqz rd to data high-z (note 1) 20 25 ns t ehel e pulse width 27 32 ns t theh r/w setup time to enable 6 10 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address (note 4) 20 25 ns output delay psd935g2 psd9xx family 69 notes: 1. rd timing has the same timing as ds and psen signals. 2. rd and psen have the same timing. 3. any input used to select an internal psd935g2 function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds signals. read timing (5 v 10% versions) microcontroller interface ? psd935g2 ac/dc parameters (5v 10% versions)
psd9xx family psd935g2 70 -70 -90 symbol parameter conditions min max min max unit t lvlx ale or as pulse width 15 20 t avlx address setup time (note 1) 4 6 ns t lxax address hold time (note 1) 7 8 ns t avwl address valid to leading edge of wr (notes 1 and 3) 8 15 ns t slwl cs valid to leading edge of wr (note 3) 12 15 ns t dvwh wr data setup time (note 3) 25 35 ns t whdx wr data hold time (note 3) 4 5 ns t wlwh wr pulse width (note 3) 28 35 ns t whax1 trailing edge of wr to address invalid (note 3) 6 8 ns t whax2 trailing edge of wr to dpld address input invalid (note 3 and 4) 0 0 ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3) 27 30 ns t avpv address input valid to address (note 2) 20 25 ns output delay write timing (5 v 10% versions) notes: 1. any input used to select an internal psd935g2 function. 2. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 3. wr timing has the same timing as e, ds signals. 4. t whax2 is address hold time for dpld inputs that are used to generate chip selects for internal psd memory. microcontroller interface ? psd935g2 ac/dc parameters (5v 10% versions) -70 -90 slew turbo rate symbol parameter conditions min max min max off (note 1) unit t pd pld input pin/feedback to 20 25 add 12 sub 2 ns pld combinatorial output t ard pld array delay 11 16 ns pld combinatorial timing (5 v 10%) note: 1. fast slew rate output available on port c and f.
psd935g2 psd9xx family 71 symbol parameter conditions min typ max unit t nlnh warm reset active low time (note 1) 150 ns t opr reset high to operational device 120 ns t nlnh-po power on reset active low time 1 ms t nlnh-a warm reset active low time (note 2) 25 s reset pin timing (5 v 10%) note: 1. t clcl is the clkin clock period. microcontroller interface ? psd935g2 ac/dc parameters (5v 10% versions) symbol parameter conditions min typ max unit t bvbh vstby detection to vstbyon output high (note 1) 20 s t bxbl v stby off detection to v stbyon output low (note 1) 20 s v stbyon timing (5 v 10%) -70 -90 symbol parameter conditions min max min max unit t lvdv ale access time from power down 80 90 ns maximum delay from apd enable using clkin input 15 * t clcl (s) (note 1) s t clwh to internal pdn valid signal power down timing (5 v 10%) note: 1. reset will not abort flash programming/erase cycles. 2. reset will abort flash programming or erase cycle. note: 1. vstbyon is measured at v cc ramp rate of 2 ms.
psd9xx family psd935g2 72 -70 -90 symbol parameter conditions min max min max unit t isccf tck clock frequency (except for pld) (note 1) 20 18 mhz t iscch tck clock high time (note 1) 23 26 ns t isccl tck clock low time (note 1) 23 26 ns t isccf-p tck clock frequency (for pld only) (note 2) 2 2 mhz t iscch-p tck clock high time (for pld only) (note 2) 240 240 ns t isccl-p tck clock low time (for pld only) (note 2) 240 240 ns t iscpsu isc port set up time 6 8 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 21 23 ns t iscpzv isc port high-impedance to valid output 21 23 ns t iscpvz isc port valid output to high-impedance 21 23 ns isc timing (5 v 10%) microcontroller interface ? psd935g2 ac/dc parameters (5v 10% versions) symbol parameter min typ max unit flash program 8.5 sec flash bulk erase (preprogrammed to 00) (note 1) 3 30 sec flash bulk erase 10 sec t whqv3 sector erase (preprogrammed to 00) 1 30 sec t whqv2 sector erase 2.2 sec t whqv1 word program 14 1200 s program/erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output valid (data polling) (note 2) 30 ns flash program, write and erase times (5 v 10%) note: 1. programmed to all zeros before erase. 2. the polling status dq7 is valid tq7vqv ns before the data dq0-7 is valid for reading. notes: 1. for ?on-pld?programming, erase or in isc by-pass mode. 2. for program or erase pld only.
psd935g2 psd9xx family 73 symbol parameter conditions min typ max unit v cc supply voltage all speeds 3.0 3.6 v v ih high level input voltage 3.0 v < v cc < 3.6 v .7 v cc v cc +.5 v v il low level input voltage 3.0 v < v cc < 3.6 v .5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v lko v cc min for flash erase and program 1.5 2.3 v v ol output low voltage i ol = 20 a, v cc = 3.0 v 0.01 0.1 v i ol = 4 ma, v cc = 3.0 v 0.15 0.45 v v oh output high voltage except v stby on i oh = 20 a, v cc = 3.0 v 2.9 2.99 v i oh = 1 ma, v cc = 3.0 v 2.7 2.8 v v oh 1 output high voltage v stby on i oh 1 = 1 a v sby ?0.8 v v sby sram standby voltage 2.0 v cc v i sby sram standby current (v stby pin) v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb standby supply current csi >v cc ?.3 v 50 100 a for power down mode (notes 2 and 3) i li input leakage current v ss < v in < v cc ? .1 1 a i lo output leakage current 0.45 < v in < v cc ?0 5 10 a i o output current refer to i ol and i oh in the v ol and v oh row pld_turbo = off, f = 0 mhz (note 3) 0ma pld only pld_turbo = on, i cc (dc) operating f = 0 mhz 200 400 a/pt (note 5) supply current during flash flash write/erase only 10 25 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma pld ac base (note 4) figure 27a i cc (ac) flash (note 5) ac adder 1.5 2.0 ma/mhz sram ac adder 0.8 1.5 ma/mhz psd935g2 dc characteristics (3.0 v to 3.6 v versions) advance information notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd mode is active. 3. pld is in non-turbo mode and none of the inputs are switching. 4. refer to figure 31a for pld current calculation. 5. i o = 0 ma.
psd9xx family psd935g2 74 ac symbols for pld timing. example: t avlx ? time from address valid to ale invalid. signal letters a address input c ceout output d input data e e input l ale input n reset input or output p port signal output q output data r wr, uds, lds, ds, iord, psen inputs s chip select input t r/w input w internal pdn signal b vstby output signal behavior t time l logic level low or ale h logic level high v valid x no longer a valid logic level z float pw pulse width microcontroller interface psd935g2 ac/dc parameters (3.0 v to 3.6 v versions)
psd935g2 psd9xx family 75 -90 -12 turbo symbol parameter conditions min max min max off unit t lvlx ale or as pulse width 22 24 ns t avlx address setup time (note 3) 7 9 ns t lxax address hold time (note 3) 8 10 ns t avqv address valid to data valid (note 3) 90 120 add 20** ns t slqv cs valid to data valid 90 120 ns rd to data valid (note 5) 35 35 ns t rlqv rd or psen to data valid, 80c51 mode (note 2) 45 48 ns t rhqx rd data hold time (note 1) 0 0 ns t rlrh rd pulse width (note 1) 36 40 ns t rhqz rd to data high-z (note 1) 38 40 ns t ehel e pulse width 38 42 ns t theh r/w setup time to enable 10 16 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to (note 4) 30 35 ns address output delay read timing (3.0 v to 3.6 v versions) microcontroller interface ? psd935g2 ac/dc parameters (3.0 v to 3.6 v versions) notes: 1. rd timing has the same timing as ds and psen signals. 2. rd and psen have the same timing for 80c51. 3. any input used to select an internal psd4135g2v function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. 5. rd timing has the same timing as ds signals.
psd9xx family psd935g2 76 -90 -12 slew turbo rate symbol parameter conditions min max min max off (note 1) unit t pd pld input pin/feedback to 38 43 add 20 sub 6 ns pld combinatorial output t ard pld array delay 23 27 ns pld combinatorial timing (5 v 10%) note: 1. fast slew rate output available on port c and f. -90 -12 symbol parameter conditions min max min max unit t lvlx ale or as pulse width 22 24 t avlx address setup time (note 1) 7 9 ns t lxax address hold time (note 1) 8 10 ns t avwl address valid to leading edge of wr (notes 1 and 3) 15 18 ns t slwl cs valid to leading edge of wr (note 3) 15 18 ns t dvwh wr data setup time (note 3) 40 45 ns t whdx wr data hold time (note 3) 5 8 ns t wlwh wr pulse width (note 3) 40 45 ns t whax1 trailing edge of wr to address invalid (note 3) 8 10 ns t whax2 trailing edge of wr to dpld address (notes 3 and 4) 0 0 ns input invalid t whpv trailing edge of wr to port output valid using i/o port data register (note 3) 33 33 ns t avpv address input valid to address (note 2) 30 35 ns output delay write timing (3.0 v to 3.6 v versions) notes: 1. any input used to select an internal psd935g2 function. 2. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 3. wr timing has the same timing as e, ds signals. 4. t whax2 is address hold time for dpld inputs that are used to generate chip selects for internal psd memory. microcontroller interface ? psd935g2 ac/dc parameters (3.0 v to 3.6 v versions)
psd935g2 psd9xx family -90 -12 symbol parameter conditions min max min max unit t lvdv ale access time from power down 128 135 ns maximum delay from apd enable t clwh to internal pdn valid signal using clkin input 15 * t clcl (s) (note 1) s power down timing (3.0 v to 3.6 v versions) symbol parameter conditions min typ max unit t nlnh warm reset active low time (note 1) 300 ns t opr reset high to operational device 300 ns t nlnh-po power on reset active low time 1 ms warm resetactive low time t nlnh-a (note 2) 25 s reset pin timing (3.0 v to 3.6 v versions) note: 1. t clcl is the clkin clock period. microcontroller interface ? psd935g2 ac/dc parameters (3.0 v to 3.6 v versions) symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1) 20 s t bxbl v stby off detection to v stbyon output low (note 1) 20 s v stbyon timing (3.0 v to 3.6 v versions) note: 1. reset will not abort flash programming/erase cycles. 2. reset will abort flash programming or erase cycle. note: 1. vstbyon is measured at v cc ramp rate of 2 ms. 77
psd9xx family psd935g2 78 microcontroller interface ? psd935g2 ac/dc parameters (3.0 v to 3.6 v versions) symbol parameter min typ max unit flash program 8.5 sec flash bulk erase (preprogrammed to 00) (note 1) 3 30 sec flash bulk erase 10 sec t whqv3 sector erase (preprogrammed to 00) 1 30 sec t whqv2 sector erase 2.2 sec t whqv1 word program 14 1200 s program/erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output valid (data polling) 30 ns (note 2) flash program, write and erase times (3.0 v to 3.6 v versions) -90 -12 symbol parameter conditions min max min max unit t isccf tck clock frequency (except for pld) (note 1) 15 12 mhz t iscch tck clock high time (note 1) 30 40 ns t isccl tck clock low time (note 1) 30 40 ns t isccf-p tck clock frequency (for pld only) (note 2) 2 2 mhz t iscch-p tck clock high time (for pld only) (note 2) 240 240 ns t isccl-p tck clock low time (for pld only) (note 2) 240 240 ns t iscpsu isc port set up time 11 12 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 26 32 ns t iscpzv isc port high-impedance to valid output 26 32 ns t iscpvz isc port valid output to high-impedance 26 32 ns isc timing (3.0 v to 3.6 v versions) notes: 1. programmed to all zeros before erase. 2. the polling status dq7 is valid tq7vqv ns before the data dq0-7 is valid for reading. notes: 1. for ?on-pld?programming, erase or in isc by-pass mode. 2. for program or erase pld only.
psd935g2 psd9xx family 79 figure 28. read timing t avlx t lxax * t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w * t avlx and t lxax are not required 80c51xa in burst mode.
psd9xx family psd935g2 80 figure 29. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale/as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w
psd935g2 psd9xx family 81 figure 30. combinatorial timing ? pld t pd gpld input gpld output figure 31. jtag-isp timing iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t
psd9xx family psd935g2 82 figure 32. reset timing figure 33. key to switching waveforms operating level power on reset v cc reset t nlnh po t opr t nlnh-a t nlnh t opr warm reset waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
psd935g2 psd9xx family 83 symbol parameter 1 conditions typical 2 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for cntl2/v pp )v pp = 0 v 18 25 pf notes: 1. these parameters are only sampled and are not 100% tested. 2. typical values are for t a = 25 c and nominal supply voltages. t a = 25 ?, f = 1 mhz 14.0 pin capacitance 15.0 figure 34. ac testing input/output waveform 16.0 figure 35. ac testing load circuit 17.0 programming 3.0v 0v test point 1.5v device under test 2.01 v 195 c l = 30 pf (including scope and jig capacitance) upon delivery from st, the psd935g2 device has all bits in the plds and memories in the 1 or high state. the configuration bits are in the 0 or low state. the code, configuration, and plds logic are loaded through the procedure of programming. information for programming the device is available directly from st. please contact your local sales representative. (see the last page.)
psd9xx family psd935g2 84 18.0 psd935g2 pin assignments pin no. pin assignments pin no. pin assignments 1 pd2 41 pc0 2 pd3 42 pc1 3 ad0 43 pc2 4 ad1 44 pc3 5 ad2 45 pc4 6 ad3 46 pc5 7 ad4 47 pc6 8 gnd 48 pc7 9v cc 49 gnd 10 ad5 50 gnd 11 ad6 51 pa0 12 ad7 52 pa1 13 ad8 53 pa2 14 ad9 54 pa3 15 ad10 55 pa4 16 ad11 56 pa5 17 ad12 57 pa6 18 ad13 58 pa7 19 ad14 59 cntl0 20 ad15 60 cntl1 21 pg0 61 pb0 22 pg1 62 pb1 23 pg2 63 pb2 24 pg3 64 pb3 25 pg4 65 pb4 26 pg5 66 pb5 27 pg6 67 pb6 28 pg7 68 pb7 29 v cc 69 v cc 30 gnd 70 gnd 31 pf0 71 pe0 32 pf1 72 pe1 33 pf2 73 pe2 34 pf3 74 pe3 35 pf4 75 pe4 36 pf5 76 pe5 37 pf6 77 pe6 38 pf7 78 pe7 39 reset 79 pd0 40 cntl2 80 pd1 80-pin plastic thin quad flatpack (tqfp) (package type u)
psd935g2 psd9xx family 85 19.0 psd935g2 package information 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 figure 36. drawing u5 ? 80-pin plastic thin quad flatpack (tqfp) (package type u)
psd9xx family psd935g2 86 figure 36a. drawing u5 ? 80-pin plastic thin quad flatpack (tqfp) (package type u) d d1 d3 e3 e1 e index mark standoff: 0.05 mm min. load coplanarity: 0.102 mm max. l c be1 a2 a a1 80 1 2 3 family: plastic thin quad flatpack (tqfp) millimeters inches symbol min max notes min max notes 0 7 0 8 a 1.20 0.047 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 reference 0.007 0.011 c 0.20 0.008 d 13.95 14.05 0.512 0.551 d1 11.95 12.05 0.433 0.472 d3 9.5 reference 0.374 reference e 13.95 14.05 0.512 0.551 e1 11.95 12.05 0.433 0.472 e3 9.5 reference 0.374 reference e1 0.50 reference 0.019 reference l 0.45 0.75 0.018 0.030 n80 80 060198r0
psd935g2 psd9xx family 87 20.0 selector guide part # mcu plds/decoders i/o memory other software 5 data inputs input macrocells ports flash program store isp via jtag psdsoft volts path output macrocells 2nd flash array iap via mcu express outputs eeprom zero power psdsoft page sram per. mode 2000 reg. w/bb security pmu apd psd935g2 8 52 24 8-bit 52 4096kb 256kb 64kb x x x x x x x x psd913f2 8 27 _ 19 8-bit 27 1024kb 256kb 16kb x x x x x x x x psd934f2 8 27 _ 19 8-bit 27 2048kb 256kb 16kb x x x x x x x x selector guide ?psd935g2 series
psd9xx family psd935g2 88 21.0 part number construction 22.0 ordering information i/o count & other nvm size sram size family/series psd brand name psd = standard low power device 8 = flash psd for 8-bit mcus 0 = 0kb 1 = 16kb 2 = 32kb 3 = 64kb 1 = 256kb 2 = 512kb 3 = 1mb 4 = 2mb 5 = 4mb revision "blank" = no rev. - a = rev. a - b = rev. b - c = rev. c speed - 70 = 70ns - 90 = 90ns - 12 = 120ns - 15 = 150ns - 20 = 200ns package type j = plcc u = tqfp m = pqfp b81 = bga temp range "blank" = 0 c to + 70 c (commercial) i = 40 c to + 85 c (industrial) 2nd nvm type, size & configuration 1 = eeprom, 256kb 2 = flash, 256kb 3 = no 2nd array v cc voltage "blank" = 5 volt v = 3.0 volt f = 27 i/o g = 52 i/o flash psd part number construction 41 = flash psd for 16-bit mucs (with simple pld) 9 = flash psd for 8-bit mucs (with simple pld) 42 = flash psd for 16-bit mucs (with cpld) i i i i i i i i i i i i i i i i i i character # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 pa rt number psd 4 2 13f2 a 15j operating speed temperature part number (ns) package type range psd935g2-70u 70 80 pin tqfp comm? psd935g2-90u 90 80 pin tqfp comm? psd935g2-90ui 90 80 pin tqfp industrial psd935g2v-90u 90 80 pin tqfp comm? psd935g2v-12u 120 80 pin tqfp comm? psd935g2v-12ui 120 80 pin tqfp industrial
psd935g2 2/3 revision history table 1. document revision history date rev. description of revision 25-feb-2000 1.0 psd935g2: document written in the wsi format. initial release 30-nov-2000 1.1 specifications changed tlxax -70 min from 5 to 7 page 70: changed turbo off from add 10 to add 12. changed tlxax -70 min from 5 to 7, changed tdvwh -70 min from 12 to 25, changed twlwh -70 min from 25 to 28. 31-jan-2002 1.2 psd935g2: configurable memory system on a chip for 8-bit microcontrollers front page, and back two pages, in st format, added to the pdf file references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express
3/3 psd935g2 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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